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october 2012 doc id 023063 rev 4 1/200 1 SPEAR1340 dual-core cortex a9 hmi embedded mpu datasheet ? preliminary data features cpu subsystem: ? 2x arm cortex a9 cores, up to 600 mhz ? 32+32 kb l1 caches per core, with parity check ? shared 512 kb l2 cache ? accelerator coherence port (acp) network-on-chip bus matrix, up to 166 mhz 32 kb boot rom, 32+4 kb static rams memory interfaces: ? ddr controller (ddr3-1066, ddr2-1066 @533mhz), 16-/32-bit, up to 2 gb address space ? serial nor flash controller ? parallel nand flash/nor flash/sram controller connectivity: ? 2 x usb 2.0 host ports (integrated phy) ? 1 x usb 2.0 otg port (integrated phy) ? 1 x giga/fast ethernet port (external gmii/ rgmii/mii/rmii phy) ? 1 x pcie 2.0 rc/ep port (integrated phy) ? 1 x 3gb/s serial ata host port (integrated phy) ? 1 x memory card interface: sd/sdio/mmc, cf/cf+, xd ? 2 x uart ports, with irda option ? 2 x i2c bus controllers, master/slave ? 1 x synchronous serial port, spi/microwire/ti protocols, master/slave ? 2 x consumer electronic control (hdmi cec) ports ? 10-bit adc: 8 ch. 1 msps, with autoscan ? programmable bidirectional gpio signals with interrupt capability hmi support: ? lcd display controller, incl.support for full hd, 1920 x 1080, 60 hz, 24 bpp ? high-perf. 2d/3d gpu, up to 1080p ? hardware video decoder: multistandard up to 1080p, jpeg ? hardware video encoder: h.264 up to 1080p, jpeg ? video input parallel port, with alternate configuration for 4 x camera interfaces ? digital audio ports: up to 7.1 multichannel surround, i2s (8 in, 8 out) and s/pdif ? 6 x 6 keyboard controller ? resistive touchscreen interface security: ? c3 cryptographic accelerator ? secure boot support ? jtag disable option miscellaneous functions: ? energy saving: power islands, clock gating, dynamic frequency scaling ? 2 x dma controllers (total 16 channels) ? 11 x general purpose timers, 2 x watchdogs, 1 x real-time clock ? 4 x pwm generators ? embedded sensor for junction temperature monitoring ? otp (one-time programmable) bits ? debug and trace interfaces: jtag/ptm table 1. device summary order code temp. range, c package packing SPEAR1340-2 -40 to 85 pbga (23x23mm, pitch 0.8mm) tr ay pbga (23 x 23 mm) www.st.com
contents SPEAR1340 2/200 doc id 023063 rev 4 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 device functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 cpu subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 multilayer interconnect matrix (busmatrix) . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 internal memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3.1 bootrom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3.2 static rams (sram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 multiport ddr controller (mpmc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 serial nor flash controller (smi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 flexible static memory controller (fsmc) . . . . . . . . . . . . . . . . . . . . . . . . 10 2.7 usb 2.0 host controllers (uhc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.8 usb 2.0 otg port (uoc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.9 giga/fast ethernet port (gmac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.10 pci express controller (pcie) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.11 serial ata controller (sata) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.12 sata/pcie physical interface (miphy) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.13 memory card interfaces (mcif) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.14 uart ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.15 i2c bus controllers (i2c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.16 synchronous serial port (ssp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.17 a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.18 hdmi cec interfaces (cec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.19 general purpose i/o (gpio/xgpio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.20 lcd display controller (clcd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.21 graphics processing unit (gpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.22 video decoder (vdec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.23 video encoder (venc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.24 camera input interfaces (cam) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.25 video input parallel port (vip) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.26 i2s digital audio ports (i2s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SPEAR1340 contents doc id 023063 rev 4 3/200 2.27 s/pdif digital audio port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.28 keyboard controller (kbd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.29 cryptographic co-processor (c3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.30 real-time clock (rtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.31 dma controllers (dmac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.32 general purpose timers (gpt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.33 pwm generators (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.34 clock and reset system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.35 reset and clock generator (rcg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.36 power control module (pcm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.37 temperature sensor (thsens) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.38 one-time programmable antifuse (otp) . . . . . . . . . . . . . . . . . . . . . . . . . 38 3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.1 pin map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.2 ball characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3 power supply signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 3.4 multiplexed signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.4.1 mac ethernet port multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . 94 3.4.2 kbd multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 3.4.3 mcif multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 3.4.4 fsmc multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 3.5 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 3.5.1 cpu subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 3.5.2 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3.5.3 clocks and resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 3.5.4 debug interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 3.5.5 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 3.5.6 audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 3.5.7 video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 3.5.8 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 3.5.9 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 3.6 strapping options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
contents SPEAR1340 4/200 doc id 023063 rev 4 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 4.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 4.3 clocking parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 4.3.1 master clock (mclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 4.3.2 real-time clock (rtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 4.4 i/o ac/dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 4.4.1 3v3/2v5/1v8 i/o buffers (iotype1/ iotype2/iotype3) . . . . . . . . . . 138 4.4.2 iotype4 i/o buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 4.4.3 ddr2 and ddr3 mode i/o buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 4.5 voltage regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 4.6 miphy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 4.7 required external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 4.8 power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 4.9 power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 4.10 reset release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 4.11 adc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 5 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 5.1 reset timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 5.2 adc timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 5.3 cortex-a9 jtag/trace timing characteristics . . . . . . . . . . . . . . . . . . . . . 152 5.3.1 cortex-a9 jtag timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . 152 5.3.2 cortex-a9 trace timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 153 5.4 cam timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 5.5 clcd timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 5.6 fsmc timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 5.6.1 nand flash configuration timing characteristics . . . . . . . . . . . . . . . . . 157 5.6.2 nor flash configuration timing characteristics . . . . . . . . . . . . . . . . . . 159 5.6.3 sram configuration timing characteristics . . . . . . . . . . . . . . . . . . . . . 162 5.7 gmac timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 5.7.1 gmii transmit timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 5.7.2 gmii receive timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 5.7.3 mii transmit timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 5.7.4 mii receive timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
SPEAR1340 contents doc id 023063 rev 4 5/200 5.7.5 mac ethernet asynchronous signals timing characteristics (mac_crs and mac_col) 167 5.7.6 mac serial management channel timing characteristics (mdio/mdc) 167 5.8 gpio/xgpio timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 5.9 i2c timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 5.10 i2s timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 5.11 mcif timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 5.11.1 synchronous mode (sd/sdio/mmc) . . . . . . . . . . . . . . . . . . . . . . . . . 172 5.11.2 compactflash true ide pio mode/udma mode . . . . . . . . . . . . . . . . . 174 5.12 mpmc timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 5.13 pwm timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 5.14 smi timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 5.15 ssp timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 5.15.1 spi master mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 5.15.2 spi slave mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 5.16 uart timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 5.16.1 irda timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 5.17 vip timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 appendix a acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 appendix b copyright statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
description SPEAR1340 6/200 doc id 023063 rev 4 1 description the SPEAR1340 device is a system -on-chip belonging to the spear ? (structured processor enhanced architecture) family of embedded microprocessors. the product is suitable for consumer and professional applications where an advanced human machine interface (hmi) combined with high performance are required, such as low-cost tablets, thin clients, media phones and industrial/printer smart panels. the device is hardware-compliant to the support of both real-time (rtos) and high-level (hlos) operating systems, such as android, linux and windows embedded compact 7. the architecture of SPEAR1340 is based on several inte rnal components, communicating through a multilayer interconnection matrix (b usmatrix). this switching structure enables different data flows to be carried out concurrently, improving the overall platform efficiency. in particular, high-performance master agents are directly interconnected with the ddr memory controller in order to reduce access latency. the overall memory bandwidth assigned to each master port can be programmed and optimized through an internal weighted round-robin (wrr) arbitration scheme. figure 1. SPEAR1340 architectural block diagram fpu ptm cortexa9cpu 32kb icache 32kb dcache interrupt controller 512kbl2cache acp cache transfers snoop filtering timer& watchdog cpu0 axibus master0 axibus master1 coresight global timer timer& watchdog cpu1 scu mpcore cpu0 displayctrl 2d/3dgpu videodecoder videoencoder camerai/f(4x) videoinput i2saudioi/f (8in,8out) s/pdifaudioi/f usb2.0hostctrl usb2.0otgctrl usb phys giga/fast ethernetctrl pcie ctrl satactrl phy graphics,video,audio highspeedconnectivity usb2.0hostctrl busmatrixinterconnect gpio xgpio i2c(2x) ssp uart(2x) kbd cec(2x) adc pwm(4x) rtc lowspeedconnectivity ddr2/3ctrl staticmemoryctrl serialmemoryi/f memorycardi/f memory fpu ptm cortexa9cpu 32kb icache 32kb dcache cpu1 bootrom srams dmactrl(2x) security coprocessor reset&clockgenerator powercontrol configuration registers timers jtag trace thsens otp opt. battery
SPEAR1340 device functions doc id 023063 rev 4 7/200 2 device functions 2.1 cpu subsystem the cpu subsystem is based on the arm co rtex a9 processor, and has a dual-core configuration. main features: each core has the following features: arm v7 cpu at 600 mhz 32 kb of l1 instruction cache with parity check 32 kb of l1 data cache with parity check embedded fpu for single and double data precision scalar floating-point operations memory management unit (mmu) arm, thumb2 and thumb2-ee instruction set support program trace macrocell (ptm) and coresight ? component for software debug 32-bit timer with 8-bit prescaler internal watchdog (working also as timer) the dual core configuration is completed by a common set of components: snoop control unit (scu) to manage inter-process communication, cache-to-cache and system memory transfer, cache coherency generic interrupt control (gic) unit configured to support 128 independent interrupt sources with software configurable priority and routing between the two cores 64-bit global timer with 8-bit prescaler accelerator coherence port (acp) parity support to detect runtime failures for other internal memories 512 kb of unified 8-way set associative l2 cache with support for ecc l2 cache controller based on pl310 ip released by arm dual asynchronous 64-bit amba 3 axi interface with possible filtering on the second one to use a single port for ddr memory access jtag interface and trace port: debug and trace can be inhibited through otp
device functions SPEAR1340 8/200 doc id 023063 rev 4 2.2 multilayer interconnect matrix (busmatrix) the multilayer interconnect matrix is the connectivity infrastructure that enables data exchange between the various blocks of the device. the busmatrix supports parallel communications between master and slave components, and ensures the maximum level of system throughput. main features: hierarchical structure to meet the requirements of different system blocks and peripherals: ? high performance low latency ? high performance medium latency ? medium performance medium/long latency ? slow peripherals and configurations power awareness through the power down request/acknowledgement of the power management module single interrupt for outband signaling 2.3 internal memories SPEAR1340 integrates tw o embedded memories: 32 kb boot rom (bootrom) static ram areas (sram) 2.3.1 bootrom bootrom refers to the on-chip 32 kb rom as well as the booting firmware pre-stored in such memory. the supported booting devices are: serial nor flash parallel nor flash nand flash usb otg uart sd/mmc the bootrom firmware selects the booting device after reset by reading the status of the strap[3:0] pins. 2.3.2 static rams (sram) a part of these memory areas is used during the bootstrap phase by bootrom firmware. after booting, all sram areas are fully available for general purpose applications. main features: 32 kb of system ram (sysram0, single port) when all power islands are switched off, sysram0 loses its data content. 4 kb of always-on ram (sysram1, single port) when all power islands ar e switched off, sysram1 ma intains its data content.
SPEAR1340 device functions doc id 023063 rev 4 9/200 2.4 multiport ddr controller (mpmc) mpmc is a high-performance multichannel memory controller able to support ddr2 and ddr3 memory devices. the multiport architecture ensures that memory is shared efficiently among different high-bandwidth client modules. main features: supports both ddr3 and ddr2 devices; wide range of memory de vice cuts supported up to 2 gb ( note: 1 ) two chip selects supported programmable memory data path size of full memory 32-bit data width or half memory 16-bit data width clock frequencies from 100 mhz to 533 mhz supported 6 axi interfaces with a data interface width of 64 bits. each port is configured with a thread id of 4 bits exclusive and locked accesses support weighted round-robin arbitration scheme support to ensure high memory bandwidth utilization dram command processing register port with an ahb interface with a data interface width of 32 bits a programmable register interface to control memory device parameters and protocols including auto pre-charge full initialization of memory on memory controller reset automatically maps user addresses to the dram memory in a contiguous block addressing starts at user address 0 and ends at the highest available address according to the size and number of dram devices present fully pipelined command, read and write data interfaces to the memory controller advanced bank look-ahead features for high memory throughput note: 1 when the 2gb address space is enabled, the acp function is not available. 2.5 serial nor flash controller (smi) the serial nor flash controller integrated in SPEAR1340 acts as an ahb slave interface (32-, 16- or 8-bit) to spi-compatible off-chip memories. smi allows the cpu to use these serial memories either as data storage or for code execution. main features: supports a group of spi-compa tible flash and eeprom devices acts always as an spi master and up to 2 spi slave memory devices are supported (through as many chip select signals), with up to 16 mb address space each. the smi clock signal ( smi_clk_o ) is generated by smi (and inputs to all slaves) using a clock provided by the ahb bus smi_clk_o can be controlled by a programmable 7-bit prescaler allowing 127 different clock frequencies.
device functions SPEAR1340 10/200 doc id 023063 rev 4 2.6 flexible static memory controller (fsmc) the flexible static memory co ntroller enables to interface ex ternal parallel flash memories as well as static rams. main features: support for parallel nand flash: ? 8-bit or 16-bit data bus ? 2 chip select signals ? no limitation on nand capacity (number of pages) ? hardware ecc (error correction code) support, correcting up to 8 errors per page (512 bytes wide) ? support for slc (single-level cell) and mlc (multi-level cell) flash devices, as far as compatible with available ecc features support for parallel nor flash: ? 8-bit or 16-bit data bus ? 26-bit address bus ? 2 chip select (cs) signals ? maximum capacity is 64 mb for each cs, hence up to 128 mb with 2 external flash devices support for asynchronous static rams (srams): ? 8-bit or 16-bit data bus ? 26-bit address bus ? 2 chip select (cs) signals ? maximum capacity is 64 mb for each cs, hence up to 128 mb with 2 external sram devices support for multiplexed nor and sram write fifo: 16 words depth, each word is 32 bits wide independent read/write timings and protocol, allowing matching the widest variety of memories and timings wait signal for timings handshake
SPEAR1340 device functions doc id 023063 rev 4 11/200 2.7 usb 2.0 host controllers (uhc) the SPEAR1340 device integrates 2 usb host in terfaces. each interf ace provides a high- speed host controller (ehci standard) and a full-speed/low-speed controller (ohci standard). the uhc has 2 physical ports (2 separate instances) that are fully compliant with the universal serial bus specification (version 2.0), and provides an interface to the industry-standard ahb bus. main features: a phy interface implementing a usb 2.0 transceiver macro-cell interface plus (utmi+) fully compliant with utmi+ specification (revision 1.0), to execute serialization and de- serialization of transmissions over the usb line either 30 mhz clock for 16-bit interface or 60 mhz for 8-bit interface supported by the utmi + phy interface a usb 2.0 host controller (uhc) connected to the ahb bus that generates the commands for the utmi+phy complies with both the enhanced host controller interface (ehci) specification (version 1.0) and the open host controller interface (ohci) specification (version 1.0a) the uhc supports the 480 mbps high-speed (hs) for usb 2.0 through an embedded ehci host controller, as well as the 12 mbps full-speed (fs) and the 1.5 mbps low- speed (ls) for usb 1.1 through one integrated ohci host controller all clock synchronization is handled within the uhc an ahb slave for each controller (1 ehci and 1 ohci), acting as programming interface to access to control and status registers an ahb master for each controller (1 ehci and 1 ohci) for data transfer to system memory, supporting 8-, 16-, and 32-bit wide data transactions on the ahb bus 32-bit ahb bus addressing 2.8 usb 2.0 otg port (uoc) main features: complies with the on-the- go supplement to the usb 2.0 specification (revision 1.3) supports the session request protocol (srp) supports the host negotiation protocol (hnp) a phy interface implementing the usb 2.0 transceiver macrocell interface (utmi+ specification, revision 1.0 (level 3)) to execute serialization and de-serialization of transmissions over the usb line unidirectional and bidirectional 16-bit utmi data bus interfaces support for the following speeds: ? high speed (hs): 480 mbps ? full speed (fs): 12 mbps ? low speed (ls): 1.5 mbps (only in host mode) both of the dma and slave-only modes are supported
device functions SPEAR1340 12/200 doc id 023063 rev 4 2.9 giga/fast ethernet port (gmac) the gmac ip provides the capability to tr ansmit and receive da ta over ethernet. main features: supports 10/100/1000 mbps data transfer rates with the following phy interfaces: ? ieee 802.3-compliant gmii/mii interface (default) to communicate with an external gigabit/fast ethernet phy ? rgmii interface to communicate with an external gigabit phy ? rmii interface (specification version 1.2 from rmii consortium) to communicate with an external fast ethernet phy (for 10/100 mbps operations only) full-duplex operation: ? ieee 802.3x flow control automatic tran smission of zero-qu anta pause frame on flow control input de-assertion ? optional forwarding of received pause control frames to the user application half-duplex operation: ? csma/cd protocol support ? flow control using back-pressure support ? frame bursting and frame extension in 1000 mbps half-duplex operation automatic crc and pad generation controllable on a per-frame basis provides options for automatic pad /crc stripping on receive frames supports a variety of flexible address filtering modes, such as: ? up to 31 48-bit sa address comparison check with masks for each byte ? 64-bit hash filter for multicast and unicast (da) addresses ? option to pass all multicast addressed frames ? promiscuous mode support to pass all frames without any filtering for network monitoring ? passes all incoming packets (per filter) with a status report programmable frame length to support standard or jumbo ethernet frames with up to 16 kb of size programmable interframe gap (ifg) (40-96 bit times in steps of 8) separate 32-bit status for transmit and receive packets ieee 802.1q vlan tag detection for reception frames self-managed dma transfers with an internal dma block separate transmission, reception, and control interfaces to the application ? the host cpu uses a 32-bit ahb (amba 2.0) slave interface to access the gmac subsystem control and status registers (csrs) ? the gmac transfers data to system memory through a 32-bit axi (amba 3.0) master interface support for network statistics with rmon/mib counters (rfc2819/rfc2665) a module for detection of lan remote wake-up frames and amd magic packet frames: power management module (pmt) a receive module for checksum off-load for received ipv4 and tcp packets encapsulated by the ethernet frame (type 1) an enhanced receive module for checking ipv4 header checksum and tcp, udp, or icmp checksum encapsulated in ipv4 or ipv6 datagrams (type 2)
SPEAR1340 device functions doc id 023063 rev 4 13/200 an enhanced module to calculate and insert ipv4 header checksum and tcp, udp, or icmp checksum in frames transmitted in store-and-forward mode. a module to support ethernet frame time stamping as de scribed in ieee 1588- 2002 and ieee 1588-2008 (sta ndard for precision networked clock synchroniz ation). sixty- four-bit time stamps are given in the transmit or receive status of each frame. mdio master interface for phy device configuration and management: station management agent (sma), mdio module supports the standard ieee p802.3az, version d2.0 for energy efficient ethernet; allows physical layers to operate in the low-power idle (lpi) mode the mac transaction level (mtl) block consists of two sets of fifos: a transmit fifo with programmable threshold capability, and a receive fifo with a programmable threshold (default of 64 bytes). the mtl block has the following features: 32-bit transaction layer block that provides a bridge between the application and the gmac single-channel transmit and receive engines synchronization for all clocks in the design (transmit, receive, and system clocks) optimization for packet-oriented transfers with frame delimiters four separate ports for system-side and gmac side transmission and reception fifo instantiation outside the top-level modul e to facilitate memory testing/instantiation 4 kb receive fifo size on reception supports receive status vectors insertion into the receive fifo after the eof transfer. this enables multiple-frame storage in the receive fifo without r equiring another fifo to store those frames configurable receive fifo threshold (default fixed at 64 bytes) in cut-through or threshold mode provides an option to filter all error frames on reception and not forward them to the application in store-and-forward mode. provides an option to forward under-sized good frames supports statistics by generating pulses for frames dropped or corrupted (due to overflow) in the receive fifo 2 kb fifo size on transmission store and forward mechanism for transmission to the gmac threshold control for transmit buffer management automatic retransmission of collision frames for transmission discards frames on late collision, excessiv e collisions, excessive deferral, and under- run conditions software control to flush tx fifo the dma block exchanges data between the mtl block and host memory. the host can use a set of registers (dma csr) to control the dma operations. the dma block supports the following features: 32-bit data transfers single-channel transmit and receive engines fully synchronous design operating on a single system clock (except for csr module, when a separate csr clock is configured) optimization for packet-oriented dma transfers with frame delimiters
device functions SPEAR1340 14/200 doc id 023063 rev 4 byte-aligned addressing for data buffer support dual-buffer (ring) or linked-list (chained) descriptor chaining descriptor architecture that allows large blocks of data transfer with minimum cpu intervention comprehensive status reporting for normal operation and transfers with errors individual programmable burst size for transmit and receive dma engines for optimal host bus utilization programmable interrupt options for different operational conditions complete per-frame transmit/receive interrupt control round-robin or fixed-priority arbitration between receive and transmit engines start/stop modes separate ports for host csr access and host data interface the gmac audio video (av) enables transmission of time-sensitive traffic over bridged local area networks (lans). the gmac av has the following features: compliant to ieee 802.1-as standard, version d6.0: sp ecifies the protocol and procedures used to ensure that the synchronization requirements are met for time- sensitive applications compliant to ieee 802.1-qav standard, version d6.0: allo ws the bridges to provide time-sensitive and loss-sensitive real-time audio video data transmission (av traffic). it specifies the priority regeneration and controlled bandwidth queue draining algorithms that are used in bridges and av traffic sources supports one additional channel (channel 1) on the transmit and receive paths for av traffic in 100 mbps and 1000 mbps modes. the channel 0 is available by default and carries the legacy best-effort ethernet traffic on the transmit side. supports ieee 802.1-qav sp ecified credit-based shaper (cbs) algorithm for the additional transmit channels provides separate dma, txfifo, and rxfifo mtl for the additional channel (to avoid ?head of line blocking? issues); the system-side interface remains the same. the gmac has the following additional features for monitoring, testing, and debugging: supports internal loopback on the gmii/mii for debugging provides dma states (tx and rx) as status bits provides debug status register that gives status of fsms in transmit and receive data- paths and fifo fill-levels application abort status bits mmc (rmon) module in the gmac core current tx/rx buffer pointer as status registers current tx/rx descriptor pointer as status registers statistical counters that help in calculating the bandwidth served by each transmit channel when av support is enabled
SPEAR1340 device functions doc id 023063 rev 4 15/200 2.10 pci express controller (pcie) the pci express core incorporates a dual-mode (dm) core which can implement a pcie interface for a pcie root complex (rc) or endpoint (ep). the dual-mode core can operate in ep or rc port modes, depending on value written in a register during pcie configuration. pcie is compliant with the pci express base 2.0 specification, but it is also compliant with the pcie 1.1 specification. the core features a proprietary user-configurable and high-performance application interface for generating and receiving pcie traffic. it is available with standard amba 3 axi interfaces. typical applications for a pci express de vice built with the dm core include: motherboard components for desktop and mobile computers graphics devices add-in cards for desktop and mobile computers components and add-in cards in server applications embedded applications data communications equipment telecommunications equipment storage devices wireless devices other applications the dm core in ep mode supports pci express legacy endpoint devices. however, the application must ensure that the device obeys the legacy endpoint device rules defined in the pci express base 2.0 specification. note: the core is not intended for use in a root complex integrated endpoint. main features (common to both ep and rc mode of the dm cores): support for all non-optional features and some optional features defined in the pci express base 2.0 specification. ultra low transmit and receive latency support a max payload size of 256 bytes 4 kb maximum request size very high accessible bandwidth support for both gen1 (at 125 mhz) and gen2 (at 250 mhz) operation 2.5 gbps (gen1) or 5.0 gbps (gen2) lane (x1) automatic lane reversal as specified in the pci express 2.0 specification (transmit and receive) polarity inversion on receive multiple virtual channel s (vcs) (maximum of 2) multiple traffic classes (tcs) ecrc generation and checking pci express beacon and wake-up mechanism
device functions SPEAR1340 16/200 doc id 023063 rev 4 pci power management pci express active state power management (aspm) pci express advanced error reporting vital product data (vpd) pcie messages for both transmit and receive. external priority arbitration (in addition to the internally implemented transmit arbitration) expansion rom support additional features specific to rc mode type 1 configuration space application-initiated lane reversal for situations where the core does not detect lane 0 (for example, an x4 core connected to an x8 device that has its lanes reversed) additional features specific to ep mode completion time-out ranges type 0 configuration space msi interrupt capability 2.11 serial ata controller (sata) the sata ahci core implements the serial advanced technology attachment (sata) storage interface for physical storage devices. main features: sata 3.0 gb/s gen ii esata (external analog logic also needs to support esata) compliant with the following specifications: ? serial ata 3.0 (except fis-based switching) ? ahci revision 1.3 (except fis-based switching) ? amba 3 axi interfaces user-defined phy status and control ports rx data buffer for recovered clock systems data alignment circuitry when rx data buffer is also included oob signaling detection and generation 8b/10b encoding/decoding asynchronous signal recove ry, including retry polling digital support of device hot-plugging power management features including automatic partial-to-slumber transition bist loopback modes single sata device internal dma engine per port hardware-assisted native command queuing for up to 32 entries
SPEAR1340 device functions doc id 023063 rev 4 17/200 port multiplier with command-based switching disabling rx and tx data clocks during power down modes integrated sata link layer and transport layer logic supports pio, first party and legacy dma modes supports legacy command queuing supports ata and atapi master-only emulation mode (for instance, register and command compatible with these standards) power-down mode data scrambling crc computation automatic data flow control far end loop-back re-timed 2.12 sata/pcie physical interface (miphy) the miphy macrocell implements the lower (physical) layer protocols providing data transmission and reception over a dual differen tial pair cable. the tx (transmit) and rx (receive) serial channels operate plesiochronously (nrz). the macrocell can be used in host or device applications. main features: serial transceiver (physical layer) serializer and deserializer direct support for 1.5/ 3.0 and 1.25/ 2.5/ 5.0 gbit/s bit rates 20-bit parallel interface comma detect to provide word alignment of incoming serial stream ssc modulation integrated impedance adaptation to transmission line characteristics out-of-band (oob) signaling supported 1.2 v and 2.5 v power supply high-performance pll (input reference 100 mhz for pcie and 100 or 25 mhz for sata) programmable tx buffer pre-emphasis, slew-rate and amplitude dedicated tx buffer regulator for: ? transmit buffer noise immunity ? buffer level stability
device functions SPEAR1340 18/200 doc id 023063 rev 4 2.13 memory card interfaces (mcif) mcif is a hardware ip that interfaces with the most common memory cards on the market: sd/sdio 2.0 sdhc cf/cf+ rev 4.1 mmc 4.2/4.3 xd the device interface multiplexes different memory cards on the same ios; only one memory card is accessible at a given time. at the board level, discrete elements are required to handle host-swap management. main features: sd/sdio/mmc controller compliant with: ? sd host controller standard specification version 2.0 ? sdio card specification version 2.0 ? sd memory card specification draft version 2.0 ? sd memory card security specification version 1.01 ? mmc specification version 3.31, 4.2 and 4.3 ? amba specification ahb (version 2.0) data transfer with the system core through: ? pio mode on the host ahb slave interface ? dma mode on the host ahb master interface host clock rate variable from 0 to 50 mhz maximum data rate achievable: ? 200 mbps (sd4 bit mode) ? 400 mbps (mmc8 bit mode) data transfer: ? sd mode: 1 bit, 4 bit, and spi mode ? mmc mode: 1 bit, 4 bit, 8 bit, and spi mode cyclic redundancy check for commands (crc7) and for data integrity (crc16) variable length data transfer read wait control and suspend/resume operations supported works with io cards, read-only cards and read/write cards supports mmc plus and mmc mobile error correction code support for mmc 4.3 cards card detection (insertion/removal) card password protection two 4k fifo to aid data transfer between the cpu and the controller fifo overrun and underrun handled by stopping the sd clock
SPEAR1340 device functions doc id 023063 rev 4 19/200 cf/cf+ host controller cf specification revision 4.1 compliance (true ide mode only) multiword dma to transfer data between the host and the cf/+ device ultra dma mode for accessing the cf/+ card using the 16-bit data path pio timing mode0 through mode6 multiword dma timing mode0 through mode4 ultra dma timing mode0 through mode6 data transfers up to 256 (512 byte) blocks variable-length data transfer in multiword dma and ultra dma modes interrupt-driven data transfers in pio mode xd host controller (xtreme digital) comfortable erase mechanism programmable access timing read, write, erase, read device id, status and reset commands ecc generation and checking multiblock programming and multiblock erase 1 gbit, 2 gbit support 2.14 uart ports the SPEAR1340 device integrates 2 instances of an asynchronous serial port (uart) digital block, identified as uart0 and uart1. asynchronous serial ports are responsible for performing the main tasks in serial communications with computers. the device converts incoming parallel information into serial data and incoming serial information into parallel data that can be sent on a communication line connected to an external peripheral device. the SPEAR1340 embedded mpu provides two in dependent uart controllers. one of the typical uses of uart is c onnecting the spear-based platfo rms to debugging consoles, the communication with modems and the interfacing of bluetooth, dect or zigbee chipsets. the uart features inside spear 1340 offer similar functional ity to the indu stry-standard 16c650 uart device. uart ports usually do not directly generate or receive the external signals used between different items of equipment. external interface devices are used to convert the logic level signals of the uart to and from the external signaling levels. external signals may be of many different forms, such as rs-232, infrared and wireless radio. in particular, the uart interfaces inside SPEAR1340 dire ctly support (by software se lection) the irda-compliant serial infrared (sir) protocol. the uart supports standard asynchronous communication bits (start, stop , and parity) , which are added prior to transmission and removed on reception.
device functions SPEAR1340 20/200 doc id 023063 rev 4 main features: uart0 and uart1: support baud rate up to uartclk/16 programmable baud rate generation (integer and fractional parts) support three options on the uartclk clock frequency: ? 48 mhz: maximum baud rate of 3 mbps (48/16) ? 24 mhz: maximum baud rate of 1.5 mbps (24/16) ? programmable by software: up to 125 mhz with a maximum baud rate of 7.81 mbps (125/16). separate 16x8 transmit and 16x12 receive first-in, first-out memory buffers (fifos) programmable fifo disabling for 1-byte depth fifo trigger levels selectable between 1/8, 1/4, 1/2, 3/4 and 7/8 independent masking of transmit fifo, receive fifo, receive time-out, and error condition interrupts support for direct memory access (dma) false start bit detection line break generation and detection programmable usage of irda sir encoder/decoder: irda sir endec block provides: ? support of irda sir endec functions for data rates up to 115.2 kbits/second half-duplex ? support of normal 3/16 and low-power bit durations ? programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration fully-programmable serial interface characteristics: ? data can be 5, 6, 7, or 8 bits ? even, odd, stick, or no-parity bit generation and detection ? 1 or 2 stop bit generation uart0 only: programmable hardware flow control which uses the cts input and the rts output to automatically control the serial data flow support modem status which uses: ? input signals: clear to send (cts), data carrier detect (dcd), data set ready (dsr), and ring indicator (ri) ? output modem control lines: request to send (rts), and data terminal ready (dtr) independent masking of modem status
SPEAR1340 device functions doc id 023063 rev 4 21/200 2.15 i2c bus controllers (i2c) the SPEAR1340 device integrates 2 instances of an i2 c controller, identified as i2c0 and i2c1, which can be used to connect to the i2c bus peripheral. main features: compliant to the i2c-bus sp ecification from philips three different operating modes: ? standard-speed mode (data rates up to 100 kb/s) ? fast-speed mode (data rates up to 400 kb/s) ? high-speed mode clock synchronization master or slave i2c operation mode multimaster operation mode (bus arbitration) support for direct memory access (dma) 7-bit or 10-bit addressing 7-bit or 10-bit combined format transfers slave bulk transfer mode ignores cbus addresses (an older ancestor of i2c that used to share the i2c bus) buffer transmission and reception interrupt or polled-mode operation handles bit and byte waiting at all bus speeds digital filter for the re ceived sda and scl lines 2.16 synchronous serial port (ssp) the synchronous serial port block includes a master or slave interface to enable synchronous serial communication with slave or master peripherals. main features: master or slave operation programmable clock bit rate and prescaler separate transmit and receive first-in, first-out memory buffers, 16-bit wide, 8 locations deep programmable choice of interface operation, spi, microwire, or ti synchronous serial programmable data frame size from 4 to 16 bits independent masking of transmit fifo, receive fifo, and receive overrun interrupts internal loopback test mode available support for direct memory access (dma)
device functions SPEAR1340 22/200 doc id 023063 rev 4 2.17 a/d converter (adc) SPEAR1340 integrates an anal og-to-digital converter. main features: successive approximation a/d conversion 10-bit resolution for the analog cell which can be extended up to 12 bits with embedded oversampling techniques performed by the controller 1 msps 8 analog input channels (0 ? 2.5 v) inl 1 lsb dnl 1 lsb programmable conversion speed ? minimum conversion time 1 s support for resistive touchscreen 2.18 hdmi cec interfaces (cec) the SPEAR1340 device integrates 2 instance s of a consumer electronics control (cec) digital block, identified as cec0 and cec1. cec is an asynchronous transfer mode adaptation layer (aal) protocol that provides high- level control functions among the various audiovisual products in a user?s environment. cec operates at low speeds, with minimal processing and memory overhead. main features: amba 2.0 compatible one touch play: play a device and make it the active source with the press of a button system standby: set all devices to standby with the press of a button preset transfer: auto-configures device presets to match those of the tv one-touch record: enables one-button recording timer programming: any device can program a recording device?s timer system information: devices can auto-configure their language and country settings deck control: a device can control and interrogate a playback device tuner control: a device can control the tuner of another device vendor specific commands: enables the use of vendor-defined commands on-screen display (osd): a device can display text on the tv screen device menu control: a device can control the menu of another device routing control: enables cec switch co ntrol, to stream a new source device remote control pass through: enables the passing on of remote control commands to other devices device osd name transfer: system devices can request the preferred object-based storage device (osd) name of other system devices
SPEAR1340 device functions doc id 023063 rev 4 23/200 2.19 general purpose i/o (gpio/xgpio) SPEAR1340 handles gene ric input/outputs in 3 ways. first, the device integr ates 2 instances of a general purpose i/o (gpio) digital block, identified as gpioa and gpiob. second, an extended gpio (xgpio) feature is provided. finally, it is possible to use the kbd controller in gpio mode (this feature is documented in section 2.28: keyboard controller (kbd) ). the gpio block provides 16 programmable inputs or outputs (8 for gpioa and 8 for gpiob). each input/output can be controlled by software. gpio main features: 16 individually programmable input/output pins (by default input at reset) an apb slave acting as contro l interface in software mode programmable interrupt generation capability on any number of pins bit masking in both read and writes operation through address lines the xgpios are individually programmable input/ output pins (by default output) that can be controlled through an ahb slave interface. xgpio main features: 234 individually programmable input/output pins: xgpio0 to xgpio7, and xgpio24 to xgpio249 (by default output). there is just an exception for the bit xgpio169 which is always an output. programmable interrupt (rise or fall edge sensitive) generation on any number of pins an ahb slave interface as control
device functions SPEAR1340 24/200 doc id 023063 rev 4 2.20 lcd display controller (clcd) the tft lcd controller provides all the necessary control signals to interface directly to a variety of tft lcd panels. main features: wide range of programmable lcd panel resolutions support for 1 port tft lcd panel interfaces: ? 18-bit digital (6-bit/color) ? 24-bit digital (8-bit/color) cmos support for 2 port tft lcd panel interfaces (2 nd port available by programmable signals) support for up to 2 overlay windows. programmable frame buffer bits-per-pixel (bpp) color depths: ? 1, 2, 4, 8 bpp mapped through the color palette to 18-bit lcd pixel ? up to 18 bpp directly drive 18-bit lcd pixel ? 24 bpp directly drive 24-bit lcd pixel color palette ram to reduce frame buffer memory storage requirements bandwidth programmable output format support: ? rgb 6:6:6 or 5:6:5 or 5:5:5 on 18-bit digital interface ? rgb 8:8:8 on 24-bit digital interface programmable horizontal timing parameters: ? horizontal front porch, back porch, sync width, pixels-per-line ? horizontal sync polarity programmable vertical timing parameters: ? vertical front porch, back porch, sync width, lines-per-panel ? vertical sync polarity programmable pixel clock frequency up to 148mhz (1080p resolution) programmable data enable timing signal: ? derived from horizontal and vertical timing parameters ? display enable polarity power up and down sequencing support programmable endianness pulse width modulation for lcd panel led backlight brightness control
SPEAR1340 device functions doc id 023063 rev 4 25/200 2.21 graphics processing unit (gpu) the mali gpu is a hardware accelerator for 2d and 3d graphics systems that forms the basis of a high performance graphics processing solution. when implemented as part of a system-on-chip (soc) device, the gpu forms an integral part of the graphics solution. the gpu comprises the following: an arm ? mali?200 pixel processor a maligp2 geometry processor a memory management unit (mmu) associated software (programmed using openvg or opengl base layers) main features (pixel processor): programmable fragment shader access to framebuffer from fragment shaders alpha blending arbitrary memory reads and writes complete non-power-of-2 texture support cube mapping dynamic recursion fast dynamic branching fast trigonometric functions, including arctangent full floating-point arithmetic framebuffer blend with destination alpha high dynamic range (hdr) textures and framebuffers indexable texture samplers line, quad, triangle, and point sprites multiple render targets no limit on program length perspective anisotropic filtering (af) perspective correct texturing point sampling, bilinear, and trilinear filtering programmable mipmap level-of-detail biasing and replacement register indirect jumps stencil buffering, 8-bit two-sided stencil unlimited dependent texture reads virtualized texture samplers 4-level hierarchical z and stencil operations 4 times and 16 times full sce ne anti-aliasing (fsaa) 4-bit per texel texture compression. geometry processor programmable vertex shader autonomous operation tile list generation flexible input and output formats indexed and non-indexed geometry input primitive constructions with points, lines, triangles and quads.
device functions SPEAR1340 26/200 doc id 023063 rev 4 software compatibility with the follo wing graphics standards: ? opengl es 2.0 ? opengl es 1.1 ? openvg 1.0 the geometry processor must be programmed using openvg or open gl base layers. 2.22 video decoder (vdec) main features: all algorithms in hardware - minimal cpu load minimal power consumption - functional level clock gating and synthesis time clock gating (> 90% of registers under gating) supported video codecs: h.264 profile and level ? baseline, main and high profiles ? decoding up to 1080p/30fps (1) scalable video coding (svc): ? baseline and high profiles (base layer only) mpeg-4 visual profile and level ? simple and advanced simple profiles, levels 0 ?5 (2) h.263 profile and level ? profile 0, levels 10 ?70 (image size up to 720x576) sorenson spark wmv9 / vc-1 ? simple, main and advanced profiles, levels 0 -3 mpeg-1&2 main profile ? low, medium and high levels realvideo8/9/10 divx?3/4/5/6 support ? home theater profile qualification vp6, vp7 versions 0-3 vp8 version 2 (webm) avs jizhun profile jpeg, all common sampling formats ? baseline interleaved 1. achievable resolution and frame rate depending on specific stream content and system load. 2. global motion compensation (gmc) is not supported.
SPEAR1340 device functions doc id 023063 rev 4 27/200 supported post-processing features: input image source ? internal source (combined mode): g1decoder ? external source (standalone mode): for example, a software decoder or camera interface input image size ? combined mode: 48 x 48 to 8176 x 8176 (66.8 mpixels) ? standalone mode: width from 48 to 8176, height from 48 to 8176 (maximum size limited to 16.7 mpixels) output image size ? 16 x 16 to 1920 x 1088 image scaling ? bicubic polynomial in terpolation for upscaling ? proprietary averaging filter for downscaling ? arbitrary, non-integer scaling ratio separately for both dimensions ycbcr to rgb color conversion ? bt.601-5 compliant ? bt.709 compliant ? user definable conversion coefficient dithering ? 2x2 ordered spatial dithering for 4-, 5- and 6-bit rgb channel precision alpha blending ? output image can be alpha blended with two rectangular areas deinterlacing ? conditional spatial deinterlace filtering; supports only ycbcr 4:2:0 input format linear rgb image contrast , brightness and color saturation adjustment deblocking filter for mpeg-4 simple profile /h.263 / sorenson ? using a modified h.264 in-loop filter as a postprocessing filter; filtering has to be performed in combined mode. image cropping / digital zoom ? user definable start position, height and width ? usable only for jpeg or stand-alone mode output image masking image rotation ? rotation 90, 180 or 270 degrees ? horizontal/vertical flip
device functions SPEAR1340 28/200 doc id 023063 rev 4 2.23 video encoder (venc) a multiformat video encoder is integrated in SPEAR1340 with 64 -bit axi master and 32-bit ahb slave interfaces. it supports h.264 high profile video resolution up to 1080p and jpeg still picture up to 64 mpixel. main features: h.264 profile and level ? baseline, main and high profiles, levels 1- 4.0 jpeg profile and level ? baseline (dct sequential) video stabilization i and p slices support cavlc baseline and cabac main profile error resilience ? constrained intra prediction ? slices, multiple of macro blocks rows maximum motion vector length ? vertical 14 pixels ? horizontal 30pixels 12 intra prediction modes motion vector pixel accuracy ? 720p resolution ? pixels ? 1080p resolution ? pixels macroblock and sub-macroblock partitions: 16x16, 8x16, 16x8, 8x8, 4x8, 8x4,4x4 transforms 4x4 baseline, main and high profiles 1 reference frame support maximum 1 slice group support input data formats ? planar ycbcr 4:2:0, semiplanar ycbcr 4:2:0, interleaved ycbcr 4:2:2 output data formats ? h.264 (byte and nal unit stream) ? jpeg( jfif file format 1.02 and non progressive jpeg) supported image size ? h.264: 96x96 to1920x1020 ? jpeg: 96x96 to 8192x8192 ? step size 4 pixels pre-processing features ? ycbcr 4:2:2 to ycbcr 4:2:0 color space conversion for all ycbcr input formats ? cropping from 8192 x 8192 to any supported encoding size ? rotation of 90 or 270 degrees
SPEAR1340 device functions doc id 023063 rev 4 29/200 2.24 camera input interfaces (cam) the SPEAR1340 device integrates 4 instances of a camera input (cam) digital block, identified as cam1, cam2, cam3, cam4. each cam interface enables spear 1340 to interface with an external image sensor. an incoming image is stored in camif memory per a programmed mode, and then transferred to external memory using system direct memory access. main features: amba 2.0 compatible slave interface with connection to external system dma 8-bit parallel data interface ycbcr4:2:2, rgb888 packed, rgb888 un-packed, rgb565, jpeg mode video mode with all running frame compliant with itu-r bt.601 (external synchronization) as well as itu-r bt.656 (embedded synchronization) image cropping programmable polarity of pixel clock and external synchronization signals (hsynch, vsynch) note: for 1080p 30 hz video maximum pixel clock frequency for cam required is (2x2200x1125x30)=148.5 mhz. 2.25 video input parallel port (vip) the video input parallel port is used to interface with some external image sensors. incoming images are stored inside its internal fifo as per some programmed mode and then transferred to the external memory through the master interface. main features: supports hdmi, dvi, dp and cvbs supports output format rgb alon g with hsync, vsync and pixel clock clock polarity configuration provided (positive edge/negative edge) hsync and vsync polarity configurable handling of data enable signal dual-port display in dvi mode for 16 bpp and 24 bpp supported input bit width 16 bpp, 24 bpp and 32 bpp supported only unpacked data format supported
device functions SPEAR1340 30/200 doc id 023063 rev 4 2.26 i2s digital audio ports (i2s) the i2s controller is a highly configurable ip for use in audio applications. it provides a simple interface to standard audio components. main features: compliant to philips i2s serial bus specifications i2s master for output operations and i2s slave for input operations configurable number of stereo channels (up to 4) for both transmitter and receiver supports up to 7.1 audio tx and rx supports 12-/16-/20-/24-/32-bit audio data interface fully synchronous design with serial clock and system clock interrupt support for reporting fifo and other conditions programmable fifo thresholds supports data exchange to the system memory through dma interface software controlled block resets and enables software controlled fifo flush 2.27 s/pdif digital audio port the s/pdif audio interface detects bi-phase encoded s/pdif signals, and plays pcm audio data or audio encoded bit streams stored in memory in the s/pdif format. main features: input fully compliant with iec-60958 for audio data supports typical audio sampling frequencies, such as 32, 44.1, 48, 96, and 192 khz. programmable dma trigger threshold vucp storage can optionally be disabled audio data can be stored in bit lengths of 16 to 24 bits output compliant with iec-60958 for audio data and iec-61937 for compressed audio data supports typical audio sampling frequencies such as 32, 44.1, 48, 96, and 192 khz supports one-bit audio mode (hdmi) supports dts-hd mode programmable system dma trigger limit programmable vucp insertion supports 16/0 or 16/16 audio data format in memory 2.28 keyboard controller (kbd) the gpio keyboard controller integrated in SPEAR1340 offers a 3-mode inpu t and output port. it provides an12-bit gpio, or 6x6 keyb oard, or 2x2 keyboard plus 8-bit gpio, and offers an interface to the industry standard apb bus.
SPEAR1340 device functions doc id 023063 rev 4 31/200 main features: amba apb interface gpio or keyboard functionality with selection of any one of the two keyboard matrices: ? 12-bit general purpose parallel port (gpio) with input or output single pin programmability ? 36 (6x6) keys keyboard ? 4 (2x2) key keyboard plus 8-bit gpio with input or output single pin programmability 2.29 cryptographic co-processor (c3) c3 is a multipurpose, instruction driven, programmable dma-based co-processor. it is configured to accelerate cryptographic and network security functions. main features: amba ahb 2.0 master and slave interfaces scatter and gather dma engine (implemented only by mpcm channel) instruction dispatchers ? id0 and id1 available ? id2 and id3 not available internal ram: 4kx32 coupling/chaining: 2 paths the hardware accelerator crypto algorithm s available in SPEAR1340 have the following channels supported by mentioned operations: channel 0 : move channel ? supported operations: copy, and, or, xor ? chained mode: either master or slave ? cascaded mode: both master and slave ? input fifo: 8x32 bits ? output fifo: 8x32 bits channel 1 : data encryption standard (des and tripledes) ? id: 0x00002001 ? supported algorithms: des (56-bit keys, ecb and cbc encryption/decryption, no parity check) and tripledes (168-bit keys, ecb and cbc encryption/decryption, encdecenc) ? input fifo: 16x32 bits ? output fifo: 16x32 bits channel 2: mpcm for the advanced encryption standard (aes) ? id: 0x0000e000 ? supported algorithms: aes (128-, 192-, 256-bit keys, ecb and cbc encryption/decryption, with programmable operation modes to support almost all possible modes, including counter and xts mode) ? memory for modes of operation: 512 words of 62 bits each ? input fifo: 16x32 bits
device functions SPEAR1340 32/200 doc id 023063 rev 4 ? output fifo: 16x32 bits ? read scatter/gather list: 4x32 bits ? write scatter/gather list: 4x32 bits channel 3: unified hash wit h hmac (uhh) ? id: 0x00004014 ? supported algorithms: hmac md5 (hash with 128-bit digest), hmac sha1 (hash with 160-bit digest) and hmac sha2 (sha256 and sha224 with 256- and 224-bit digest respectively) ? input fifo: 16x32 bits ? output fifo: 8x32 bits channel 4 : unified hash 2 with hmac (uhh2) ? id: 0x00011001 ? supported algorithms: hmac sha384 (hash with 384-bit digest) and hmac sha512 (hash with 512-bit digest) ? input fifo: 16x32 bits ? output fifo: 8x32 bits channel 5 : public key accelerator (pka) v6 ? id: 0x00006001 ? supported algorithms: modular exponentiation for rsa and diffie-hellman (up to 2048 bits), scalar multiplicatio n of elliptic curve points over prime fields for ecc (up to 384 bits) and montgomery?s parameter for finite field operations ? input fifo: 8x32 bits ? output fifo: 8x32 bits channel 6 : random number generator (rng) ? id: 0x0000f000 ? generates a sequence of true random numbers, based on a contiguous analog oscillator; the sequence has a success ra tio of more than 85 % for 20.000 bits, according to fips 140-1 tests ? monitors the entropy of the generated sequence ? input fifo: 2x32 bits ? output fifo: 4x32 bits channel 7 : empty 2.30 real-time clock (rtc) the rtc is a block that keeps track of the real time of day. it also functions as an alarm and a calendar. the time is displayed in 24-hour format, and time/calendar values are stored in binary-coded decimal format. the time of day, alarm and calendar, status and control registers can all be accessed via a standard 32 apb bus. a ll read/write operatio ns last 2 cycles. rtc provides a self-isolation mode that is activated during power down. this allows rtc to continue its operation (except for the alarm interrupt feature that is not preserved) if power is not supplied to the rest of the circuit. this feature is realized by supplying separate power and clock connections.
SPEAR1340 device functions doc id 023063 rev 4 33/200 a set of 16 general purpose registers (gp-reg) are provided which can be used to save data during the power down state. gp-reg-set runs on 32 k oscillator clock and powered by rtc battery. each register is of 32 bits a nd addressed mapped on th e 32-bit apb bus. a bit in status register reflects the status of any pending write to gp-reg-set. this means that write operation to the gp-reg-set should be sequential, so you should wait for this pending status bit to be cleared before writing again to gp-reg-set. main features: works on dedicated 32768 hz external clock and power supply 9999- year calendar leap years support programmable alarm interrupt power management and self-isolation prescaler and timer registers bypass for test time and date update monitors 16 general purpose registers which can be used to save data during power down state 2.31 dma controllers (dmac) the SPEAR1340 device integrates 2 instances of a dma controller (dmac) digital block, identified as dmac0 and dmac . the dmac is an ahb-central dma controller core that transfers data from a source peripheral to a destination peripheral over two ahb buses. a wrapper is designed to instantiate 2 dmac cores (each with 2 ahb master interfaces), 2 icms (which arbitrate the same master interface of each dmac) and a mux (which manages multiple peripheral handshaking interfaces). main features: amba 2.0-compliant ahb slave interface ? used to program the dmac 8 channels, one per source and destination pair unidirectional channels ? data transfers in one direction only programmable channel priority 2 independent ahb master interfaces data bus width configured to 64 bits for each ahb master interface configurable endianness for master interfaces support for memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral dma transfers component id parameters for configurable software driver support programmable source and destination addresses (on ahb bus) address increment, decrement or no change multiblock transfers achieved through linked lists (block chaining) independent source and destination selection of multiblock transfer type scatter/gather
device functions SPEAR1340 34/200 doc id 023063 rev 4 single fifo per channel for source and destination fifo depth configured to 16 bytes for the first 4 channels and to 128 bytes for the last 4 channels d flip-flop-based fifo automatic data packing or unpacking to fit fifo width programmable source and destination for each channel programmable transfer type for each channel (memory-to-memory, memory-to- peripheral, peripheral-to-memory, and peripheral-to-peripheral) programmable burst transaction size for each channel programmable enable and disable of dma channel support for disabling channel without data loss support for suspension of dma operation support for retry, split, and error responses programmable maximum burst transfer size per channel maximum transaction size configured to 256 for all the channels maximum block size configured to 4095 for all the channels bus locking ? can be programmed to be over the transaction, block, or dma transfer level channel locking ? can be programmed to be over the transaction, block, or dma transfer level 16 handshaking interfaces for source and destination peripherals hardware and software handshaking interfaces peripheral interrupt handshaking interface handshaking interface supports single or burst dma transactions polarity control for hardware handshaking interface enabling and disabling of individual dma handshaking interface programmable flow control at block transfer level (source, destination or dmac core) software control of source data pre-fetch when destination is flow controller combined and separate interrupt requests interrupt generation on dma transfer (multiblock) completion, block transfer completion, single and burst transaction completion and error condition support of interrupt enabling and masking.
SPEAR1340 device functions doc id 023063 rev 4 35/200 2.32 general purpose timers (gpt) the SPEAR1340 device integrates 4 instances of a general purpose timer (gpt) digital block, identified as gpt0, gpt1, gpt2, gpt3. each instance is a dual timer, for total 8 independent timers. general purpose timers can be used for prec ise timing measurement and for measurement of frequency of any input signal. they are essentially counters that increment based on the clock cycle and the timer prescaler. an application can monitor these counters to determine how much time has elapsed. gpt can ha ve timer and captur e mode capabilities. main features: it is constituted by 2 channels; each one consists of a programmable 16-bit counter and a dedicated 4-bit timer clock prescaler the programmable 4-bit prescaler unit performs a clock division by 1, 2, 4, 8, 16, 32, 64, 128 and 256 three interrupt sources (match, redg, and fedg) are available for each timer channel. they are mapped to a single interrupt line for each channel but may be individually masked and acknowledged each timer has a separate register set to control, enable and run each channel separately three modes of operations are available for each timer channel: ? auto-reload mode ? single-shot mode ? capture function 2.33 pwm generators (pwm) the pwm is a pulse-width modulation (pwm) timer module with four independent channels (pwm1, pwm2, pwm3, and pwm4). all four chan nels are functionally identical. using a 16-bit counter, each pwm channel generates a rectangular output pulse with programmable duty factor (0 to 100%) and frequency. the four channels can work either synchronously or asynchronously. main features: four independent pwm channels synchronous and asynchronous working modes prescaler to define the input clock frequency for each timer programmable duty factor from 0 to 100% programmable pulse frequency apb slave interface for programming registers apb clock (pclk ~ 83 mhz) as the prescaler source clock
device functions SPEAR1340 36/200 doc id 023063 rev 4 2.34 clock and reset system this centralized structure provides system synchronization. main features: six plls. four of them are fully programmable and offer an emi reduction mode (spread spectrum clock generation through dithering) that can replace all traditional emi reduction techniques. ? pll1 programmable dithered pll, dedicated for core1 & 2 & axi/ahb bus & peripherals. both core need to run at the same speed ? pll2 programmable dithered pll, dedicated for the 125 mhz clock of the gigabit ethernet mac ? pll3 programmable dithered pll, for specific embedded ip functions ? pll4 programmable dithered pll, dedicated for the ddr memory controller (asynchronous access memory mode) ? pll5 low jitter, dedicated for the usb ? pll6 for the pcie controllers several synthesizers provide different frequencies for different ips fully programmable control of clock and reset signals for all slave blocks allowing sophisticated power management. 2.35 reset and clock generator (rcg) the reset and clock generator (rcg) provides the system clocks and resets. it is highly configurable through the miscellaneous registers. main features: three main clock sources: ? osci1: 24 mhz clock coming from internal oscillator connected to external quartz ? osci2: 32 khz clock coming from internal oscillator used for rtc block (optional) ? osci3: 25/100 mhz clock coming from miphy macro (optional) three programmable dithered plls (to reduce emi): ? pll1: primarily used to generate the 1 ghz clock for the amba subsystem ? pll2, pll3: primarily used to generate clocks for generic ips seven configurable clock generators: ? sscg1-4: used by generic ips ?sscg5: for cpu clock ? sscg6: for clcd clock ? sscg7: for ahb, apb clocks three operating modes for amba clocks: ? doze: the clock source is osci2 (osci1 after power on) ? slow: the clock source is the osci1 or a divided version ? normal: the clock source is pll1 (by default), pll2, pll3 or sscg7 configurable clock gating and software reset for most peripherals global software reset and watchdog reset
SPEAR1340 device functions doc id 023063 rev 4 37/200 2.36 power control module (pcm) pcm is the core of the SPEAR1340 leakage po wer management system. its role is to properly manage the power supply shutoff of the switchable sections of the embedded mpu. main features: generation of supply switch contro l signals for SPEAR1340 power islands generation of isolatio n control signals for SPEAR1340 power islands generation of shutoff commands for external ddr 1v2 and 1v5/1v8 supply lines acknowledge generation for user requested power island configuration monitoring of voltage detector outputs for each power island wake-up source management 2.37 temperature sensor (thsens) the thsens block is an embedded sensor for junction temperature monitoring. main features: embeds a thermal sensor providing digital measurement of junction temperature generates a ?high-temperature? interrupt when junction temperature exceeds a software programmable higher bound threshold generates a ?low-temperature? interrupt when junction temperature is lower than a software programmable lower bound threshold supports operating conditions ranging from ?40 to 125 c allows measurement of junction temperature starting at 20 c allows offset correction of digital measurement (typical correction value 10) software programmable power-down functionality for lower power consumption continuous (periodic) sensing of temperature when not powered down
device functions SPEAR1340 38/200 doc id 023063 rev 4 2.38 one-time programmable antifuse (otp) the otp block is an array of one-time programmable antifuse memory cells. all otp banks feature an embedded charge pump which provides internally the high voltage necessary for antifuse programming sessions. therefore, it is not necessary to use an additional high voltage pad at the chip interface. otp is software programmable, so no dedicated programming interface is needed at chip level. main features: otp embeds three 255-bit banks, with these features: bank 1: 255-bit data bank with write-protect mechanism bank 2: 255-bit data bank with write-protect mechanism bank m: 255-bit bank, logically partitioned as follows: ? 32 bits (16 + redundancy) used for bank1/bank2 write protection ? 213 bits bootrom controlled ? 2 bits reserved ? 2 bits reserved for disabling test access to otp ? 2 bits reserved for disabling jtag access ? 4 bits bootrom controlled
SPEAR1340 pin description doc id 023063 rev 4 39/200 3 pin description this chapter provides a full description of the ball characteristics and the signal multiplexing of SPEAR1340 device. section 3.1 shows the pin map of SPEAR1340. section 3.2 shows the association between balls and pads providing a detailed description of their terminal characteristics. section 3.3 describes the power supply pins. section 3.4 shows the multiplexing scheme for multiplexed ips. section 3.5 describes the pinout for each ip, categorized by functionality. section 3.6 describes the strapping options configuration and the hardware boot selection. the following table explains the table headers and abbreviations used in this chapter. note: in this chapter ?na? stands for ?not applicable?. table 2. headers/abbreviations header description abbreviations ball ball number associated with each signal on the package. ? pin name name of signals multiplexed on each ball. note that at reset and after reset release, all i/o pads (except for usb) are in input. to choose between the possible configurations, you need to program each ip by software. please refer to section 3.4: multiplexed signals description and SPEAR1340 reference manuals for more information. ? signal type signal information (direction, type) i= input o= output io= input/output s= depending on strapping option d= open drain pwr= power supply gnd= ground z= high-impedance
pin description SPEAR1340 40/200 doc id 023063 rev 4 pin type pad type information ana= analog osc= oscillator sstl= sstl 1v5/1v8 iotype1= 3v3 iotype2= 3v3/1v8 iotype3= 3v3/2v5 iotype4= 3v3 ttl buffer reg out= voltage regulator output ana ref= analog reference ded gnd= dedicated ground pu/pd indicates the presence of an internal pull-up or pull-down resistor. pull-up and pull-down can be enabled or disabled via software. pu= pull-up pd= pull-down deact= deactivated drive drive current capability ? slew signal transition fast= fast slew nom= nominal slew direction indicates the direction of the pad. i= input o= output io= input/output out value indicates the electrical value on the ball. 0= the buffer drives v ol 1= the buffer drives v oh h= high-impedance with an active pull-up resistor l= high-impedance with an active pull-down resistor z= high-impedance supply name the voltage supply that powers the pad. see table 4: power supply signals description . ? reset state indicates the state during reset ? reset rel. state indicates the state after reset ? reset mode io voltage setting during reset ? reset rel. mode io voltage setting after reset ? compensation cell compensation cell for reducing the spread of pvt (process, voltage and temperature) related parameters of the i/o pad. the compensation values are programmable in the registers of the related cell. cc1= io_comp1_3v3 cc2= io_comp2_3v3 cc3= io_comp1_1v8_3v3 cc4= io_comp2_1v8_3v3 cc5= io_comp_2v5_3v3 cc6= io_comp_ddr table 2. headers/abbreviations (continued) header description abbreviations
SPEAR1340 pin description doc id 023063 rev 4 41/200 3.1 pin map the following figures show the pin map of the device in four quadrants (a, b, c and d). figure 2. SPEAR1340 pin map (quadrant a) 1234567891011121314 a rtc_xo ain4 ain3 ain0 adc_ vrefp gnd mclk_xi mclk_xo fsmc_io7/ xg p i o 2 3 8 fsmc_rstp wdwn1/ kbd_col4/ gpio_a2 fsmc_io13/k bd_row5/x gpio5 fsmc_io8/ kbd_row0/x gpio0 usb_uoc_d rvvbus mc i f _ data2_sd/ xgpio229 b rtc_xi ain5 ain6 ain1 adc_ vrefn gnd mc lk_ avdd1v2 mclk_ avdd3v3 fsmc_io6/ xg p i o 2 3 9 fsmc_io2/ xgpio233 fsmc_io14/k bd_col0/xg pio6 fsmc_io9/ kbd_row1/x gpio1 usb_uhc0_ drvvbus mc i f _ data3_sd/ xgpio230 c rtc_ vdd1v5 ain7 ain2 adc_ avdd2v5 adc_agnd fsmc_ce0n/ xgpio249 fsmc_rwpr t0n/ xg p i o 24 6 fsmc_ale_a d17/ xgpio243 fsmc_io5/ xg p i o 2 4 0 fsmc_io1/ xgpio234 fsmc_io15/k bd_col1/xg pio7 fsmc_io10/k bd_row2/x gpio2 usb_uhc1_ drvvbus mc i f _ data4/ xgpio231 d usb_uhc1_ dp usb_uhc1_ dm usb_uhc1_ vdd3v3 pll2_ vdd1v2 gnd pll1_ vdd1v2 fsmc_rb0/x gpio247 fsmc_ren/x gpio244 fsmc_io4/ xg p i o 2 4 1 fsmc_io0/ xgpio235 fsmc_ce1n/ kbd_col2/g pio_a0 fsmc_io11/k bd_row3/x gpio3 usb_uhc0_ overcur mc i f _ data5/ xgpio232 e usb_ analog_ test usb_uhc1_ vdd1v2 usb_uhc1_ vdd2v5 pll2_ avdd2v5 gnd pll1_ avdd2v5 fsmc_cle_a d16/ xg p i o 24 8 fsmc_wen/ xgpio245 fsmc_io3/ xg p i o 2 4 2 fsmc_rst pwdwn0/ xgpio236 fsmc_ rwprt1n/ kbd_col3/ gpio_a1 fsmc_io12/k bd_row4/ xg p i o 4 usb_uhc1_ overcur mc i f _ data0/ xgpio237 f usb_uoc_d p usb_uoc_d m usb_uoc_v bus usb_uoc_ id gnd vreg2_ 2v5_out gnd io_ vdd1v8_ 3v3 io_ vdd1v8 _3v3 gnd io_ vdd1v8 _3v3_1 io_ vdd1v8 _3v3_1 gnd io_ vdd3v3 g usb_ txrtune usb_uoc_v dd3v3 usb_uoc_v dd2v5 gnd gnd gnd h usb_uhc0_ dp usb_uhc0_ dm usb_ vssac usb_uoc_ vdd1v2 gnd vreg2 _3v3_in j mi ph y 0_ vssr miph y 0_ vssr usb_uhc0_ vdd3v3 usb_uhc0_ vdd2v5 gnd gnd k mi ph y 0_ rxn miph y 0_ rxp mi ph y 0_ vssr usb_uhc0_ vdd1v2 gnd vreg1_ 3v3_in gnd io_comp_ gnd1_ 1v8_3v3 io_comp_ rext1_ 1v8_3v3 vdd1v2 io_comp_ gnd2_ 1v8_3v3 l mi ph y 0_ vssr miph y 0_ vssr mi ph y 0_ vddr1v2 gnd gnd gnd vdd1v2 gnd vdd1v2 gnd vdd1v2 m mi ph y 0_ txn miph y 0_ txp mi ph y 0_ vssr vdd1v2 gnd vreg1_ 2v5_out gnd vdd1v2 gnd gnd gnd n mi ph y 0_ vddt1v2 miph y 0_ vdd pll1v2 mi ph y 0_ vsst gnd pll3_ avdd2v5 gnd vdd1v2 gnd vdd1v2 gnd gnd p mi ph y 0_ xta l 2 miph y 0_ xtal 1 mi ph y 0_ vdd2 pll2v5 mi ph y 0_ vsspll gnd pll3_ vdd1v2 gnd vdd1v2 gnd gnd gnd
pin description SPEAR1340 42/200 doc id 023063 rev 4 figure 3. SPEAR1340 pin map (quadrant b) 15 16 17 18 19 20 21 22 23 24 25 26 27 28 a mcif_addr1 _cle_clk/ xg p i o 2 2 5 mcif_leds/ xg p i o 2 1 9 mcif_ncd_ xd/ xg p i o 2 1 4 fsmc_ad4/m cif_ncd_ cf1/ xg p i o 2 0 9 fsmc_ad9/ mc i f _nr es et_cf/ xg p i o 2 0 4 fsmc_ad14/ mc i f _nd mac k_nwp/ xg p i o 1 9 9 fsmc_ad21/ mc i f _ data14/ xgpio194 lcd_xb5/ arm_ trcdata29/ xg p i o 1 8 9 lcd_xb0/ arm_ trcdata24/ xgpio184 lcd_xg3/ arm_ trcdata19/ xgpio179 lcd_xg0/ arm_ trcdata15/ xgpio175 lcd_r3/ arm_ tr c d ata11/ xgpio171 lcd_r6/ arm_ trcdata10/ xgpio170 lcd_r7/ arm_ tr c d ata5/ xg p i o 1 6 5 b mc i f _ data7/ xg p i o 2 2 4 mc i f _ data1/ xg p i o 2 2 0 fsmc_ad0/ mcif_ addr2/ xg p i o 2 1 5 fsmc_ad5/ mcif_ncd_ cf2/ xg p i o 2 1 0 fsmc_ad10/ mcif_ncs0_ nce/ xg p i o 2 0 5 fsmc_ad15/ mcif _ data10/ xg p i o 2 0 0 fsmc_ad22/ mc i f _ data13/ xgpio195 lcd_xb6/ arm_ trcdata30/ xg p i o 1 9 0 lcd_xb1/ arm_ trcdata25/ xgpio185 lcd_xg4/ arm_ trcdata20/ xgpio180 lcd_xg1/ arm_ trcdata16/ xgpio176 lcd_r0/ arm_ tr c d ata12/ xgpio172 lcd_vsync/ arm_ trcdata8/ xgpio168 lcd_pe/ arm_ tr c d ata4/ xg p i o 1 6 4 c mcif_ncd_ sd _mmc / xg p i o 2 2 6 mcif_data2/ xg p i o 2 2 1 fsmc_ad1/ mcif_nce_ cf/ xg p i o 2 1 6 fsmc_ad6 /mcif_data_ dir/ xg p i o 2 1 1 fsmc_ad11/ mc i f _c f _ intr/ xg p i o 2 0 6 fsmc_ad18/ mc i f _d ata9/ xg p i o 2 0 1 fsmc_ad23/ mc i f _ data12/ xgpio196 lcd_xb7/ arm_ trcdata31/ xg p i o 1 9 1 lcd_xb2/ arm_ trcdata26/ xgpio186 lcd_xg5/ arm_ trcdata21/ xgpio181 lcd_xg2/ arm_ trcdata17/ xgpio177 lcd_hsync /arm_ tr c d ata13/ xgpio173 lcd_r1/ arm_ trcdata7/ xgpio167 lcd_de/ arm_ tr c d ata3/ xg p i o 1 6 3 d mcif_dmar q_rnb_wp/ xg p i o 2 2 7 mcif_data3/ xg p i o 2 2 2 fsmc_ad2/ mcif_nce_ xd/ xg p i o 2 1 7 fsmc_ad7/ mc i f _ niord_nre/ xg p i o 2 1 2 fsmc_ad12/ mc i f _i or d y /xgpio207 fsmc_ad19/ mc i f _d ata8/ xg p i o 2 0 2 fsmc_ad24/ mc i f _ data11/ xgpio197 fsmc_ad25/ xg p i o 1 9 2 lcd_xb3/ arm_ trcdata27/ xgpio187 lcd_xg6/ arm_ trcdata22/ xgpio182 lcd_led_p wm/arm_ trcdata18/ xgpio178 lcd_xr7/ arm_ tr c d ata14/ xgpio174 lcd_r4/ arm_ trcdata6/ xgpio166 lcd_r5/ arm_ tr c d ata1/ xg p i o 1 6 1 e mcif_data1 _sd/ xg p i o 2 2 8 mcif_data6/ xg p i o 2 2 3 mc i f _sd _ cmd/ xg p i o 2 1 8 mc i f _ addr0_ale/ xg p i o 2 1 3 fsmc_ad3/ mc i f _nc e_ sd_mmc/ xg p i o 2 0 8 fsmc_ad8/ mcif_nio wr_nwe/ xg p i o 2 0 3 fsmc_ad13/ mcif_ncs1/ xgpio198 fsmc_ad20/ mc i f _ data15/ xg p i o 1 9 3 lcd_xb4/ arm_ trcdata28/ xgpio188 lcd_xg7/ arm_ trcdata23/ xgpio183 lcd_g0/ arm_ trcdata0/ xgpio160 lcd_xr0/ arm_ trcctl/ xgpio159 lcd_xr3/ arm_trccl k/xgpio158 lcd_g1/ xg p i o 1 5 7 f io_vdd3v3 gnd io_vdd3v3 io_vdd3v3 gnd io_vdd3v3 io_vdd3v3 gnd io_vdd3v3 lcd_r2/ arm_ trcdata2/ xgpio162 lcd_g4/ xgpio156 lcd_g6/ xgpio155 lcd_xr1/ xgpio154 lcd_xr4/ xg p i o 1 5 3 g io_vdd3v3 lcd_g2/ xgpio152 lcd_g5/ xgpio151 lcd_g7/ xgpio150 lcd_xr2/ xgpio149 lcd_xr5/ xg p i o 1 4 8 h gnd lcd_g3/ xgpio147 lcd_b1/ xgpio146 lcd_b0/ xgpio145 lcd_b7/ xgpio144 lcd_xr6/ xg p i o 1 4 3 j io_vdd3v3 lcd_b6/ xgpio138 lcd_b2/ xgpio142 lcd_b3/ xgpio141 lcd_b4/ xgpio140 lcd_b5/ xg p i o 1 3 9 k io_comp_ rext2_1v8_3 v3 gnd vdd1v2 gnd io_comp_ rext2_3v3 gnd cec1/ xgpio136 cec0/ xgpio135 spdif_out/x gpio137 i2c0_sda/ xgpio133 lcd_pclk/ arm_ tr c d ata9/ xg p i o 1 6 9 l gnd vdd1v2 gnd vdd1v2 io_comp_ gnd2_3v3 io_vdd2v5_ 3v3 mac_txen/ x gpio129 mac _txer / x gpio130 mac_crs/xg pio131 ssp_ss3n/ xgpio132 i2c0_scl/ xg p i o 1 3 4 m gnd gnd vdd1v2 gnd vdd1v2 gnd mac_rxd6/x gpio124 mac_rxd7/x gpio125 mac_col/ xgpio126 mac_rxdv/x gpio127 mac _r xer / x gpio128 n gnd gnd gnd vdd1v2 gnd io_vdd2v5_ 3v3 mac_rxd3/x gpio119 mac_rxd4/x gpio120 mac_rxd5/x gpio121 mac _md c / x gpio122 mac _md i o/ x gpio123 p gnd gnd vdd1v2 gnd io_comp_ rext_2v5_ 3v3 gnd io_vdd2v5_ 3v3 mac_rxd2/x gpio118 mac _txd 6/ x gpio115 mac_txd7/x gpio116 mac _ rxclk/ xg p i o 1 1 7
SPEAR1340 pin description doc id 023063 rev 4 43/200 figure 4. SPEAR1340 pin map (quadrant c) 1234567891011121314 r miphy 0_ref gnd mi ph y 0_ vssr gnd mi ph y _ vreg_ 3v3_in gnd vdd1v2 gnd vdd1v2 gnd gnd t ddr_addr8 ddr_ resetn ddr_cke gnd gnd ddrio_ vdd1v8_1v5 gnd vdd1v2 gnd gnd gnd u ddr_cs1n ddr_odt1 ddr_addr0 ddr_addr9 ddrio_ vdd1v8_1v5 gnd ddrphy_ vdd1v2 gnd ddrphy_ vdd1v2 gnd gnd v ddr_addr7 ddr_addr2 ddr_addr3 ddr_ addr11 gnd ddrio_ vdd1v8_1v5 gnd ddrphy_ vdd1v2 gnd ddrphy_ vdd1v2 gnd w ddr_addr5 ddr_addr1 ddr_ba1 ddr_ addr14 ddrio_ vdd1v8_1v5 gnd ddrphy_ vdd1v2 gnd ddrphy_ vdd1v2 gnd vdd1v2 y ddr_ addr13 ddr_addr4 ddr_ba0 ddr_addr6 gnd ddrio_ vdd1v8_1v5 aa ddr_ba2 ddr_ addr12 ddr_ addr10 ddr_wen ddrio_ vdd1v8_1v5 gnd ab ddr_clkp2 ddr_clkm2 ddr_cs0n gnd gnd ddrio_ vdd1v8_1v5 ac ddr_clkp1 ddr_clkm1 ddr_odt0 ddrio_vre f ddr_pll_ avdd2v5 gnd ddrio_ vdd1v8_1v5 gnd ddrio_ vdd1v8_1v5 gnd ddrio_ vdd1v8_1v5 gnd ddrio_ vdd1v8_1v5 gnd ad ddr_clkp0 ddr_clkm0 ddr_rasn ddr_casn ddrio_ comp_rext ddrio_ vdd1v8_1v5 gnd ddrio_ vdd1v8_1v5 gnd ddrio_ vdd1v8_1v5 gnd ddrio_ vdd1v8_1v5 gnd ddrio_ vdd1v8_1v5 ae ddr_dq4 ddr_dq6 ddr_dqs0p ddr_dq7 ddr_dm0 ddr_dq5 ddr_dq20 ddr_dq16 ddr_dqs2p ddr_dq17 ddr_dq19 test4 test3 test2 af ddr_dq2 ddr_dq0 ddr_dqs0n ddr_dq1 ddr_dq3 ddr_dq22 ddr_dq18 ddr_dqs2n ddr_dq23 ddr_dm2 ddr_dq21 test1 test0 ddr2n_ddr3 ag ddr_dq11 ddr_dq13 ddr_dm1 ddr_dqs1n ddr_dq12 ddr_dq27 ddr_dq31 ddr_dm3 ddr_dqs3n ddr_dq28 ddr_dq26 reserv ed reserv ed reserv ed ah ddr_dq15 ddr_dq9 ddr_dq8 ddr_dqs1p ddr_dq14 ddr_dq10 ddr_dq29 ddr_dq25 ddr_dq24 ddr_dqs3p ddr_dq30 reserv ed reserv ed reserv ed
pin description SPEAR1340 44/200 doc id 023063 rev 4 figure 5. SPEAR1340 pin map (quadrant d) 15 16 17 18 19 20 21 22 23 24 25 26 27 28 r gnd gnd gnd vdd1v2 io_comp_g nd_2v5_3v3 io_vdd2v5_ 3v3 mac _ rxd1/ xgp i o 11 4 mac _ txd 4/ xgpio110 mac_ txd 5/ xg p i o 1 1 1 mac _ rxd0/ xgpio112 mac_ gtxclk/ xgpio113 t gnd gnd vdd1v2 gnd vdd1v2 gnd io_vdd2v5_ 3v3 mac _ txd 3/ xgpio109 mac_ txd 1/ xg p i o 1 0 6 mac _ txd 2/ xgpio107 mac _gtxc l k125/ xgpio108 u gnd gnd gnd vdd1v2 otp_ vdd2v5 io_vdd3v3 i2s_out_ws / xg p i o 9 8 i2s_out_ data3/ xgpio100 i2s_out_ data1/ xg p i o 1 0 1 mac _ txd 0/ xgpio105 mac_ txc lk/ xgpio104 v vdd1v2 gnd vdd1v2 gnd vdd1v2 gnd i2s_in_ws/ xg p i o 9 4 i2s_out_ data2/ xgpi o 95 i2s_out_ data0/ xgpi o96 i2s_out_ refclk/ xgpio102 i2s_out_ov rsamp_clk/ xgpio103 w gnd vdd1v2 gnd vdd1v2 gnd io_vdd3v3 i2s_in_ data2/ xg p i o 9 1 i2s_in_ data1/ xgpi o 92 i2s_in_ data0/ xgpi o93 i2s_out_ bitclk/ xg p i o 9 7 i2s_in_ bitclk/ xg p i o 9 9 y gnd uart0_ txd / xg p i o 8 6 uart0_ rxd/ xgpi o 87 uart1_ txd/ xgpi o88 uart1_ rxd/ xg p i o 8 9 i2s_in_ data3/ xg p i o 9 0 aa io_vdd3v3 ssp_mosi/ xg p i o 8 1 ssp_miso/ xgpi o 82 ssp_sck/ xgpi o83 smi_cs0n/ xg p i o 8 4 touch_xy_ sel/ ssp_ss2n/ xg p i o 8 5 ab gnd smi_dataou t/ xg p i o 7 6 smi_data in/ xgpi o 77 smi_cs1n/ xgpi o79 ssp_ss0n/ xg p i o 8 0 smi_clk/ xg p i o 7 8 ac io_vdd3v3 gnd io_vdd3v3 gnd io_vdd3v3 gnd io_comp_ rext1_3v3 io_comp_ gnd1_3v3 io_vdd3v3 vip_r11/ cam1_data3 /xgpio71 vip_g4/ cam1_data1 /xgpio72 vip_g3/ cam1_ vsync/ xgpi o73 vip_hsync/ cam1_ hsync/ xg p i o 7 4 vip_r12/ cam1_ data5/ xg p i o 7 5 ad arm_tdi arm_tck spdif_in/ gpio_b3 vip_b15/ cam4_ vsync/ gpio_b4 vip_b11/ cam4_ hsync/ xg p i o 2 6 vip_b12/ cam4_data0 /xgpio27 vip_b8/ cam4_data7 /xgpio31 vip_b4/ xg p i o 3 6 vip_b5/ xg p i o 4 1 vip_r10/ cam1_data4 /xgpio66 vip_g5/ cam1_data2 /xgpio67 vip_g2/ cam1_data0 /xgpio68 vip_r13/ cam1_data6 / xg p i o 7 0 vip_pixclk/ cam1_ pixclk/ xg p i o 6 9 ae arm_trstn arm_tms uart0_dtrn /gpt1_ tmr_cpt1/ gpio_a6 pwm2/ kbd_col5/ gpio_b1/ gpio_wkup_tr ig pwm1/ ssp_ss1n/ xg p i o 2 4 vip_b13/ cam4_data1 /xgpio28 vip_g15/ cam4_data6 /xgpio32 vip_b3/ xg p i o 3 7 vip_b2/ xg p i o 4 2 vip_r1/ cam3_ vsy nc/ xg p i o 4 9 vip_r7/ cam3_data1 /xgpio53 vip_g1/ cam2_data1 /xgpio63 vip_vsy nc/ cam2_ vsync/ xg p i o 6 4 vip_r14/ cam1_data7 /xgpio65 af mresetn arm_tdo uart0_rtsn /gpt1_tmr_ cpt2/ gpio_a3 uart0_ctsn /gpt0_ tmr_clk1/ gpio_b0 pwm3/ gpt0_tmr_ cpt1/ gpio_b5/ ddrphy_vdd1 v2_off vip_b14/ cam4_data2 /xgpio29 vip_g14/ cam4_data5 /xgpio33 vip_r4/ xg p i o 3 8 vip_r5/ xg p i o 4 3 vip_r6/ cam3_data0 /xgpio48 vip_b0/ cam3_data2 /xgpio52 vip_r8/ cam2_data5 /xgpio56 vip_r9/ cam2_data4 /xgpio61 vip_g6/ cam2_data2 /xgpio62 ag reserv ed reserv ed uart0_rin/ gpt0_tmr_ cpt2/ gpio_a4 uart0_dcd n/gpt1_ tmr_clk2/ gpio_a7 pwm4/ gpt0_tmr_ clk2/ gpio_b6/ ddrio_vdd1v8 _1v5_off vip_b9/ cam4_data3 /xgpio30 vip_g13/ cam4_data4 /xgpio34 vip_g11/ xg p i o 4 0 vip_r2/ cam3_ hsync/ xg p i o 4 4 vip_b1/ cam3_data3 /xgpio47 vip_b7/ cam3_data4 /xgpio51 vip_g8/ cam2_data7 /xgpio55 vip_de/ cam2_ hsync/ xg p i o 5 9 vip_r15/ cam2_data6 /xgpio60 ah reserv ed reserv ed uart0_dsrn /gpt1_ tmr_clk1/ gpio_a5 i2c1_sda/ gpio_b2 i2c1_scl/ gpio_b7 vip_b10/ cam4_pixcl k/xgpio25 vip_g12/ xgpi o35 vip_r3/ cam3_ pixclk/ xg p i o 3 9 vip_g10/ cam3_data7 /xgpio45 vip_b6/ cam3_data5 /xgpio46 vip_g9/ cam3_data6 /xgpio50 vip_r0/ cam2_pixcl k/xgpio54 vip_g7/ cam2_data3 /xgpio57 vip_g0/ cam2_data0 /xgpio58
SPEAR1340 pin description doc id 023063 rev 4 45/200 3.2 ball characteristics ta bl e 3 provides a detailed description of SPEAR1340 pads and their terminal characteristics. two levels of multiplexing are available: pad-level multiplexing ip-level multiplexing figure 6 shows an overview of SPEAR1340 multiplexing scheme. figure 6. SPEAR1340 mu ltiplexing scheme 1. the multiplexed ips are: gmac, keyboard, mcif and fsmc. see section 3.4: multiplexed signals description for more details. p a d config u re the pad_function_en_x mi s cell a neo us regi s ter s to s elect b etween gpio/xgpio or s h a red ip s . gpio/xgpio s h a red ip s gpio/xgpio s elected s h a red ip ss elected config u re the pad_ s hared_ip_1 mi s cell a neo us regi s ter to s elect b etween ip pin 1 or ip pin 2. ip pin s elected in c as e of m u ltiplexed ip s (1) , config u re the ip- s pecific mi s cell a neo us regi s ter s to s elect which of the a v a il ab le mode s to us e. p a d-level m u ltiplexing ip-level m u ltiplexing
SPEAR1340 pin description doc id 023063 rev 4 46/200 table 3. ball characteristics ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew u3 ddr_addr0 o sstl na na na ddrio_vdd1 v8_1v5 o 0 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 w2 ddr_addr1 o sstl na na na ddrio_vdd1 v8_1v5 o 0 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 v2 ddr_addr2 o sstl na na na ddrio_vdd1 v8_1v5 o 0 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 v3 ddr_addr3 o sstl na na na ddrio_vdd1 v8_1v5 o 0 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 y2 ddr_addr4 o sstl na na na ddrio_vdd1 v8_1v5 o 0 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 w1 ddr_addr5 o sstl na na na ddrio_vdd1 v8_1v5 o 0 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 y4 ddr_addr6 o sstl na na na ddrio_vdd1 v8_1v5 o 0 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 v1 ddr_addr7 o sstl na na na ddrio_vdd1 v8_1v5 o 0 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 t1 ddr_addr8 o sstl na na na ddrio_vdd1 v8_1v5 o 0 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 u4 ddr_addr9 o sstl na na na ddrio_vdd1 v8_1v5 o 0 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 aa3 ddr_addr10 o sstl na na na ddrio_vdd1 v8_1v5 o 0 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 v4 ddr_addr11 o sstl na na na ddrio_vdd1 v8_1v5 o 0 na na na ddr2n_ddr3 ddr2n_ddr3 cc6
pin description SPEAR1340 47/200 doc id 023063 rev 4 aa2 ddr_addr12 o sstl na na na ddrio_vdd1 v8_1v5 o 0 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 y1 ddr_addr13 o sstl na na na ddrio_vdd1 v8_1v5 o 0 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 w4 ddr_addr14 o sstl na na na ddrio_vdd1 v8_1v5 o 0 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 ad3 ddr_rasn o sstl na na na ddrio_vdd1 v8_1v5 o 1 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 ad4 ddr_casn o sstl na na na ddrio_vdd1 v8_1v5 o 1 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 aa4 ddr_wen o sstl na na na ddrio_vdd1 v8_1v5 o 1 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 ab3 ddr_cs0n o sstl na na na ddrio_vdd1 v8_1v5 o 1 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 u1 ddr_cs1n o sstl na na na ddrio_vdd1 v8_1v5 o 1 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 y3 ddr_ba0 o sstl na na na ddrio_vdd1 v8_1v5 o 0 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 w3 ddr_ba1 o sstl na na na ddrio_vdd1 v8_1v5 o 0 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 aa1 ddr_ba2 o sstl na na na ddrio_vdd1 v8_1v5 o 0 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 t3 ddr_cke o sstl na na na ddrio_vdd1 v8_1v5 o 0 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 ac3 ddr_odt0 o sstl na na na ddrio_vdd1 v8_1v5 o 0 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
SPEAR1340 pin description doc id 023063 rev 4 48/200 u2 ddr_odt1 o sstl na na na ddrio_vdd1 v8_1v5 o 0 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 ae5 ddr_dm0 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ag3 ddr_dm1 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 af10 ddr_dm2 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ag8 ddr_dm3 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ah16 reserved io sstl na na na ddrio_vdd1 v8_1v5 na na na na na na na na ae3 ddr_dqs0p io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 af3 ddr_dqs0n io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ah4 ddr_dqs1p io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ag4 ddr_dqs1n io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ae9 ddr_dqs2p io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 af8 ddr_dqs2n io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ah10 ddr_dqs3p io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
pin description SPEAR1340 49/200 doc id 023063 rev 4 ag9 ddr_dqs3n io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ag14 reserved io sstl na na na ddrio_vdd1 v8_1v5 na na na na na na na na ah14 reserved io sstl na na na ddrio_vdd1 v8_1v5 na na na na na na na na af2 ddr_dq0 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 af4 ddr_dq1 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 af1 ddr_dq2 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 af5 ddr_dq3 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ae1 ddr_dq4 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ae6 ddr_dq5 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ae2 ddr_dq6 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ae4 ddr_dq7 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ah3 ddr_dq8 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ah2 ddr_dq9 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
SPEAR1340 pin description doc id 023063 rev 4 50/200 ah6 ddr_dq10 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ag1 ddr_dq11 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ag5 ddr_dq12 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ag2 ddr_dq13 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ah5 ddr_dq14 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ah1 ddr_dq15 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ae8 ddr_dq16 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ae10 ddr_dq17 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 af7 ddr_dq18 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ae11 ddr_dq19 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ae7 ddr_dq20 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 af11 ddr_dq21 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 af6 ddr_dq22 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
pin description SPEAR1340 51/200 doc id 023063 rev 4 af9 ddr_dq23 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ah9 ddr_dq24 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ah8 ddr_dq25 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ag11 ddr_dq26 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ag6 ddr_dq27 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ag10 ddr_dq28 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ah7 ddr_dq29 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ah11 ddr_dq30 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ag7 ddr_dq31 io sstl na na na ddrio_vdd1 v8_1v5 inananana ddr2n_ddr3 ddr2n_ddr3 cc6 ag13 reserved io sstl na na na ddrio_vdd1 v8_1v5 na na na na na na na na ah13 reserved io sstl na na na ddrio_vdd1 v8_1v5 na na na na na na na na ag16 reserved io sstl na na na ddrio_vdd1 v8_1v5 na na na na na na na na ah12 reserved io sstl na na na ddrio_vdd1 v8_1v5 na na na na na na na na table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
SPEAR1340 pin description doc id 023063 rev 4 52/200 ag15 reserved io sstl na na na ddrio_vdd1 v8_1v5 na na na na na na na na ag12 reserved io sstl na na na ddrio_vdd1 v8_1v5 na na na na na na na na ah15 reserved io sstl na na na ddrio_vdd1 v8_1v5 na na na na na na na na t2 ddr_resetn o sstl na na na ddrio_vdd1 v8_1v5 o 0 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 ad2 ddr_clkm0 o sstl na na na ddrio_vdd1 v8_1v5 o 1 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 ad1 ddr_clkp0 o sstl na na na ddrio_vdd1 v8_1v5 o 0 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 ac2 ddr_clkm1 o sstl na na na ddrio_vdd1 v8_1v5 o 1 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 ac1 ddr_clkp1 o sstl na na na ddrio_vdd1 v8_1v5 o 0 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 ab2 ddr_clkm2 o sstl na na na ddrio_vdd1 v8_1v5 o 1 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 ab1 ddr_clkp2 o sstl na na na ddrio_vdd1 v8_1v5 o 0 na na na ddr2n_ddr3 ddr2n_ddr3 cc6 a4 ain0 i ana na na na adc_avdd2v 5 inananana na na na b4 ain1 i ana na na na adc_avdd2v 5 inananana na na na c3 ain2 i ana na na na adc_avdd2v 5 inananana na na na table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
pin description SPEAR1340 53/200 doc id 023063 rev 4 a3 ain3 i ana na na na adc_avdd2v 5 inananana na na na a2 ain4 i ana na na na adc_avdd2v 5 inananana na na na b2 ain5 i ana na na na adc_avdd2v 5 inananana na na na b3 ain6 i ana na na na adc_avdd2v 5 inananana na na na c2 ain7 i ana na na na adc_avdd2v 5 inananana na na na af15 mresetn i iotype1 pu 10ma fast io_vdd3v3 i na pu 10ma fast 3v3 3v3 cc1 af14 ddr2n_ddr3 i iotype1 pu 10ma fast io_vdd3v3 i na pu 10ma fast 3v3 3v3 cc1 a1 rtc_xo io osc na na na rtc_vdd1v5 na na na na na na na na b1 rtc_xi i osc na na na rtc_vdd1v5 na na na na na na na na d1 usb_uhc1_dp io ana na na na usb_uhc1_v dd3v3 na na na na na na na na d2 usb_uhc1_dm io ana na na na usb_uhc1_v dd3v3 na na na na na na na na h1 usb_uhc0_dp io ana na na na usb_uhc0_v dd3v3 na na na na na na na na h2 usb_uhc0_dm io ana na na na usb_uhc0_v dd3v3 na na na na na na na na f1 usb_uoc_dp io ana na na na usb_uoc_v dd3v3 na na na na na na na na table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
SPEAR1340 pin description doc id 023063 rev 4 54/200 f2 usb_uoc_dm io ana na na na usb_uoc_v dd3v3 na na na na na na na na f4 usb_uoc_id i ana na na na usb_vdd2v5 na na na na na na na na f3 usb_uoc_vbus io ana na na na 5v na na na na na na na na e1 usb_analog_test io ana na na na usb_vdd2v5 na na na na na na na na a8 mclk_xo io osc na na na mclk_avdd3 v3 na na na na na na na na a7 mclk_xi i osc na na na mclk_avdd3 v3 na na na na na na na na m2 miphy0_txp o ana na na na miphy0_vdd t1v2 na na na na na na na na m1 miphy0_txn o ana na na na miphy0_vdd t1v2 na na na na na na na na k2 miphy0_rxp i ana na na na miphy0_vdd r1v2 na na na na na na na na k1 miphy0_rxn i ana na na na miphy0_vdd r1v2 na na na na na na na na p2 miphy0_xtal1 i osc na na na miphy0_vdd pll1v2 na na na na na na na na p1 miphy0_xtal2 io osc na na na miphy0_vdd pll1v2 na na na na na na na na af13 test0 i iotype1 pd 10ma fast io_vdd3v3 i l pd 10ma fast 3v3 3v3 cc1 af12 test1 i iotype1 pd 10ma fast io_vdd3v3 i l pd 10ma fast 3v3 3v3 cc1 ae14 test2 i iotype1 pd 10ma fast io_vdd3v3 i l pd 10ma fast 3v3 3v3 cc1 ae13 test3 i iotype1 pd 10ma fast io_vdd3v3 i l pd 10ma fast 3v3 3v3 cc1 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
pin description SPEAR1340 55/200 doc id 023063 rev 4 ae12 test4 i iotype1 pd 10ma fast io_vdd3v3 i l pd 10ma fast 3v3 3v3 cc1 ae15 bsd_trstn arm_trstn i iotype1 pu 10ma fast io_vdd3v3 i na pu 10ma fast 3v3 3v3 cc1 ad16 bsd_tck arm_tck i iotype1 pu 10ma fast io_vdd3v3 i na pu 10ma fast 3v3 3v3 cc1 ae16 bsd_tms arm_tms i iotype1 pu 10ma fast io_vdd3v3 i na pu 10ma fast 3v3 3v3 cc1 ad15 bsd_tdi arm_tdi i iotype1 pu 10ma fast io_vdd3v3 i na pu 10ma fast 3v3 3v3 cc1 af16 bsd_tdo arm_tdo io iotype1 dea ct 10ma fast io_vdd3v3 i na dea ct 10ma fast 3v3 3v3 cc1 a13 usb_uoc_drvvbus o iotype1 dea ct 10ma fast io_vdd3v3 i na dea ct 10ma fast 3v3 3v3 cc2 b13 usb_uhc0_drvvbus o iotype1 dea ct 10ma fast io_vdd3v3 o 0 dea ct 10ma fast 3v3 3v3 cc2 c13 usb_uhc1_drvvbus o iotype1 dea ct 10ma fast io_vdd3v3 o 0 dea ct 10ma fast 3v3 3v3 cc2 d13 usb_uhc0_overcur i iotype1 pu 10ma fast io_vdd3v3 i na pu 10ma fast 3v3 3v3 cc2 e13 usb_uhc1_overcur i iotype1 pu 10ma fast io_vdd3v3 i na pu 10ma fast 3v3 3v3 cc2 a12 fsmc_io8 kbd_row0 xgpio0 io iod io iotype2 pu/ pd 4/6/8/ 10ma slow /fast io_vdd1v8_3 v3 i na pu 6ma fast 1v8 strap5 cc4 b12 fsmc_io9 kbd_row1 xgpio1 io iod io iotype2 pu/ pd 4/6/8/ 10ma slow /fast io_vdd1v8_3 v3 i na pu 6ma fast 1v8 strap5 cc4 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
SPEAR1340 pin description doc id 023063 rev 4 56/200 c12 fsmc_io10 kbd_row2 xgpio2 io iod io iotype2 pu/ pd 4/6/8/ 10ma slow /fast io_vdd1v8_3 v3 i na pu 6ma fast 1v8 strap5 cc4 d12 fsmc_io11 kbd_row3 xgpio3 io iod io iotype2 pu/ pd 4/6/8/ 10ma slow /fast io_vdd1v8_3 v3 i na pu 6ma fast 1v8 strap5 cc4 e12 fsmc_io12 kbd_row4 xgpio4 io iod io iotype2 pu/ pd 4/6/8/ 10ma slow /fast io_vdd1v8_3 v3 i na pu 6ma fast 1v8 strap5 cc4 a11 fsmc_io13 kbd_row5 xgpio5 io iod io iotype2 pu/ pd 4/6/8/ 10ma slow /fast io_vdd1v8_3 v3 i na pu 6ma fast 1v8 strap5 cc4 b11 fsmc_io14 kbd_col0 xgpio6 io iotype2 pu/ pd 4/6/8/ 10ma slow /fast io_vdd1v8_3 v3 i na pu 6ma fast 1v8 strap5 cc4 c11 fsmc_io15 kbd_col1 xgpio7 io iotype2 pu/ pd 4/6/8/ 10ma slow /fast io_vdd1v8_3 v3 i na pu 6ma fast 1v8 strap5 cc4 d11 fsmc_ce1n kbd_col2 gpio_a0 io iotype2 pu/ pd 4/6/8/ 10ma slow /fast io_vdd1v8_3 v3 i na pu 6ma fast 1v8 strap5 cc4 e11 fsmc_rwprt1n kbd_col3 gpio_a1 io iotype2 pu/ pd 4/6/8/ 10ma slow /fast io_vdd1v8_3 v3 i na pu 6ma fast 1v8 strap5 cc4 a10 fsmc_rstpwdwn1 kbd_col4 gpio_a2 io iotype2 pu/ pd 4/6/8/ 10ma slow /fast io_vdd1v8_3 v3 i na pu 6ma fast 1v8 strap5 cc4 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
pin description SPEAR1340 57/200 doc id 023063 rev 4 af17 uart0_rtsn gpt1_tmr_cpt2 gpio_a3 o i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ag17 uart0_rin gpt0_tmr_cpt2 gpio_a4 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ah17 uart0_dsrn gpt1_tmr_clk1 gpio_a5 i o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ae17 uart0_dtrn gpt1_tmr_cpt1 gpio_a6 o i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ag18 uart0_dcdn gpt1_tmr_clk2 gpio_a7 i o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 af18 uart0_ctsn gpt0_tmr_clk1 gpio_b0 i o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ae18 pwm2 kbd_col5 gpio_b1 gpio_wkup_trig o io io i iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ah18 i2c1_sda gpio_b2 iod io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ad17 spdif_in gpio_b3 i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
SPEAR1340 pin description doc id 023063 rev 4 58/200 ad18 vip_b15 cam4_vsync gpio_b4 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 af19 pwm3 gpt0_tmr_cpt1 gpio_b5 ddrphy_vdd1v2_off o i io o iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ag19 pwm4 gpt0_tmr_clk2 gpio_b6 ddrio_vdd1v8_1v5_off o o io o iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ah19 i2c1_scl gpio_b7 iod io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ae19 pwm1 ssp_ss1n xgpio24 strap0 o o io s iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ah20 vip_b10 cam4_pixclk xgpio25 strap1 i i io s iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ad19 vip_b11 cam4_hsync xgpio26 strap2 i i io s iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
pin description SPEAR1340 59/200 doc id 023063 rev 4 ad20 vip_b12 cam4_data0 xgpio27 strap3 i i io s iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ae20 vip_b13 cam4_data1 xgpio28 strap4 i i io s iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 af20 vip_b14 cam4_data2 xgpio29 strap5 i i io s iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ag20 vip_b9 cam4_data3 xgpio30 strap6 i i io s iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ad21 vip_b8 cam4_data7 xgpio31 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ae21 vip_g15 cam4_data6 xgpio32 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 af21 vip_g14 cam4_data5 xgpio33 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
SPEAR1340 pin description doc id 023063 rev 4 60/200 ag21 vip_g13 cam4_data4 xgpio34 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ah21 vip_g12 xgpio35 i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ad22 vip_b4 xgpio36 i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ae22 vip_b3 xgpio37 i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 af22 vip_r4 xgpio38 i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ah22 vip_r3 cam3_pixclk xgpio39 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ag22 vip_g11 xgpio40 i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ad23 vip_b5 xgpio41 i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ae23 vip_b2 xgpio42 i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 af23 vip_r5 xgpio43 i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ag23 vip_r2 cam3_hsync xgpio44 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
pin description SPEAR1340 61/200 doc id 023063 rev 4 ah23 vip_g10 cam3_data7 xgpio45 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ah24 vip_b6 cam3_data5 xgpio46 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ag24 vip_b1 cam3_data3 xgpio47 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 af24 vip_r6 cam3_data0 xgpio48 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ae24 vip_r1 cam3_vsync xgpio49 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ah25 vip_g9 cam3_data6 xgpio50 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ag25 vip_b7 cam3_data4 xgpio51 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 af25 xgpio52 vip_b0 cam3_data2 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ae25 vip_r7 cam3_data1 xgpio53 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
SPEAR1340 pin description doc id 023063 rev 4 62/200 ah26 vip_r0 cam2_pixclk xgpio54 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ag26 vip_g8 cam2_data7 xgpio55 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 af26 vip_r8 cam2_data5 xgpio56 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ah27 xgpio57 vip_g7 cam2_data3 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ah28 vip_g0 cam2_data0 xgpio58 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ag27 vip_de cam2_hsync xgpio59 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ag28 vip_r15 cam2_data6 xgpio60 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 af27 vip_r9 cam2_data4 xgpio61 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 af28 vip_g6 cam2_data2 xgpio62 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
pin description SPEAR1340 63/200 doc id 023063 rev 4 ae26 vip_g1 cam2_data1 xgpio63 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ae27 vip_vsync cam2_vsync xgpio64 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ae28 vip_r14 cam1_data7 xgpio65 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ad24 vip_r10 cam1_data4 xgpio66 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ad25 vip_g5 cam1_data2 xgpio67 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ad26 vip_g2 cam1_data0 xgpio68 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ad28 vip_pixclk cam1_pixclk xgpio69 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ad27 vip_r13 cam1_data6 xgpio70 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ac24 vip_r11 cam1_data3 xgpio71 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
SPEAR1340 pin description doc id 023063 rev 4 64/200 ac25 vip_g4 cam1_data1 xgpio72 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ac26 vip_g3 cam1_vsync xgpio73 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ac27 vip_hsync cam1_hsync xgpio74 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ac28 vip_r12 cam1_data5 xgpio75 i i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ab24 smi_dataout xgpio76 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ab25 smi_datain xgpio77 i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ab28 smi_clk xgpio78 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ab26 smi_cs1n xgpio79 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 ab27 ssp_ss0n xgpio80 io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 aa24 ssp_mosi xgpio81 io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 aa25 ssp_miso xgpio82 io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
pin description SPEAR1340 65/200 doc id 023063 rev 4 aa26 ssp_sck xgpio83 io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 aa27 smi_cs0n xgpio84 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 aa28 touch_xy_sel ssp_ss2n xgpio85 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 y24 uart0_txd xgpio86 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 y25 uart0_rxd xgpio87 i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 y26 uart1_txd xgpio88 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 y27 uart1_rxd xgpio89 i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 y28 i2s_in_data3 xgpio90 i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 w24 i2s_in_data2 xgpio91 i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 w25 i2s_in_data1 xgpio92 i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 w26 i2s_in_data0 xgpio93 i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 v24 i2s_in_ws xgpio94 i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
SPEAR1340 pin description doc id 023063 rev 4 66/200 v25 i2s_out_data2 xgpio95 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 v26 i2s_out_data0 xgpio96 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 w27 i2s_out_bitclk xgpio97 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 u24 i2s_out_ws xgpio98 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 w28 i2s_in_bitclk xgpio99 i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 u25 i2s_out_data3 xgpio100 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 u26 i2s_out_data1 xgpio101 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 v27 i2s_out_refclk (1) xgpio102 i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 v28 i2s_out_ovrsamp_clk xgpio103 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc1 u28 mac_txclk xgpio104 i io iotype3 pu/ pd 4/6/8/ 10ma slow /fast io_vdd2v5_3 v3 i na pu 6ma fast 2v5 strap6 cc5 u27 mac_txd0 xgpio105 o io iotype3 pu/ pd 4/6/8/ 10ma slow /fast io_vdd2v5_3 v3 i na pu 6ma fast 2v5 strap6 cc5 t26 mac_txd1 xgpio106 o io iotype3 pu/ pd 4/6/8/ 10ma slow /fast io_vdd2v5_3 v3 i na pu 6ma fast 2v5 strap6 cc5 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
pin description SPEAR1340 67/200 doc id 023063 rev 4 t27 mac_txd2 xgpio107 o io iotype3 pu/ pd 4/6/8/ 10ma slow /fast io_vdd2v5_3 v3 i na pu 6ma fast 2v5 strap6 cc5 t28 mac_gtxclk125 xgpio108 i io iotype3 pu/ pd 4/6/8/ 10ma slow /fast io_vdd2v5_3 v3 i na pu 6ma fast 2v5 strap6 cc5 t25 mac_txd3 xgpio109 o io iotype3 pu/ pd 4/6/8/ 10ma slow /fast io_vdd2v5_3 v3 i na pu 6ma fast 2v5 strap6 cc5 r25 mac_txd4 xgpio110 o io iotype3 pu/ pd 4/6/8/ 10ma slow /fast io_vdd2v5_3 v3 i na pu 6ma fast 2v5 strap6 cc5 r26 mac_txd5 xgpio111 o io iotype3 pu/ pd 4/6/8/ 10ma slow /fast io_vdd2v5_3 v3 i na pu 6ma fast 2v5 strap6 cc5 r27 mac_rxd0 xgpio112 i io iotype3 pu/ pd 4/6/8/ 10ma slow /fast io_vdd2v5_3 v3 i na pu 6ma fast 2v5 strap6 cc5 r28 mac_gtxclk xgpio113 o io iotype3 pu/ pd 4/6/8/ 10ma slow /fast io_vdd2v5_3 v3 i na pu 6ma fast 2v5 strap6 cc5 r24 mac_rxd1 xgpio114 i io iotype3 pu/ pd 4/6/8/ 10ma slow /fast io_vdd2v5_3 v3 i na pu 6ma fast 2v5 strap6 cc5 p26 mac_txd6 xgpio115 o io iotype3 pu/ pd 4/6/8/ 10ma slow /fast io_vdd2v5_3 v3 i na pu 6ma fast 2v5 strap6 cc5 p27 mac_txd7 xgpio116 o io iotype3 pu/ pd 4/6/8/ 10ma slow /fast io_vdd2v5_3 v3 i na pu 6ma fast 2v5 strap6 cc5 p28 mac_rxclk xgpio117 i io iotype3 pu/ pd 4/6/8/ 10ma slow /fast io_vdd2v5_3 v3 i na pu 6ma fast 2v5 strap6 cc5 p25 mac_rxd2 xgpio118 i io iotype3 pu/ pd 4/6/8/ 10ma slow /fast io_vdd2v5_3 v3 i na pu 6ma fast 2v5 strap6 cc5 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
SPEAR1340 pin description doc id 023063 rev 4 68/200 n24 mac_rxd3 xgpio119 i io iotype3 pu/ pd 4/6/8/ 10ma slow /fast io_vdd2v5_3 v3 i na pu 6ma fast 2v5 strap6 cc5 n25 mac_rxd4 xgpio120 i io iotype3 pu/ pd 4/6/8/ 10ma slow /fast io_vdd2v5_3 v3 i na pu 6ma fast 2v5 strap6 cc5 n26 mac_rxd5 xgpio121 i io iotype3 pu/ pd 4/6/8/ 10ma slow /fast io_vdd2v5_3 v3 i na pu 6ma fast 2v5 strap6 cc5 n27 mac_mdc xgpio122 o io iotype3 pu/ pd 4/6/8/ 10ma slow /fast io_vdd2v5_3 v3 i na pu 6ma fast 2v5 strap6 cc5 n28 mac_mdio xgpio123 io iotype3 pu/ pd 4/6/8/ 10ma slow /fast io_vdd2v5_3 v3 i na pu 6ma fast 2v5 strap6 cc5 m24 mac_rxd6 xgpio124 i io iotype3 pu/ pd 4/6/8/ 10ma slow /fast io_vdd2v5_3 v3 i na pu 6ma fast 2v5 strap6 cc5 m25 mac_rxd7 xgpio125 i io iotype3 pu/ pd 4/6/8/ 10ma slow /fast io_vdd2v5_3 v3 i na pu 6ma fast 2v5 strap6 cc5 m26 mac_col xgpio126 i io iotype3 pu/ pd 4/6/8/ 10ma slow /fast io_vdd2v5_3 v3 i na pu 6ma fast 2v5 strap6 cc5 m27 mac_rxdv xgpio127 i io iotype3 pu/ pd 4/6/8/ 10ma slow /fast io_vdd2v5_3 v3 i na pu 6ma fast 2v5 strap6 cc5 m28 mac_rxer xgpio128 i io iotype3 pu/ pd 4/6/8/ 10ma slow /fast io_vdd2v5_3 v3 i na pu 6ma fast 2v5 strap6 cc5 l24 mac_txen xgpio129 o io iotype3 pu/ pd 4/6/8/ 10ma slow /fast io_vdd2v5_3 v3 i na pu 6ma fast 2v5 strap6 cc5 l25 mac_txer xgpio130 o io iotype3 pu/ pd 4/6/8/ 10ma slow /fast io_vdd2v5_3 v3 i na pu 6ma fast 2v5 strap6 cc5 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
pin description SPEAR1340 69/200 doc id 023063 rev 4 l26 mac_crs xgpio131 i io iotype3 pu/ pd 4/6/8/ 10ma slow /fast io_vdd2v5_3 v3 i na pu 6ma fast 2v5 strap6 cc5 l27 ssp_ss3n xgpio132 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 k27 i2c0_sda xgpio133 iod io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 l28 i2c0_scl xgpio134 iod io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 k25 cec0 xgpio135 io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 k24 cec1 xgpio136 io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 k26 spdif_out xgpio137 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 j24 lcd_b6 xgpio138 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 j28 lcd_b5 xgpio139 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 j27 lcd_b4 xgpio140 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 j26 lcd_b3 xgpio141 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 j25 lcd_b2 xgpio142 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
SPEAR1340 pin description doc id 023063 rev 4 70/200 h28 lcd_xr6 xgpio143 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 h27 lcd_b7 xgpio144 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 h26 lcd_b0 xgpio145 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 h25 lcd_b1 xgpio146 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 h24 lcd_g3 xgpio147 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 g28 lcd_xr5 xgpio148 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 g27 lcd_xr2 xgpio149 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 g26 lcd_g7 xgpio150 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 g25 lcd_g5 xgpio151 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 g24 lcd_g2 xgpio152 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 f28 lcd_xr4 xgpio153 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 f27 lcd_xr1 xgpio154 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
pin description SPEAR1340 71/200 doc id 023063 rev 4 f26 lcd_g6 xgpio155 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 f25 lcd_g4 xgpio156 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 e28 lcd_g1 xgpio157 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 e27 lcd_xr3 arm_trcclk xgpio158 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 e26 lcd_xr0 arm_trcctl xgpio159 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 e25 lcd_g0 arm_trcdata0 xgpio160 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 d28 lcd_r5 arm_trcdata1 xgpio161 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 f24 lcd_r2 arm_trcdata2 xgpio162 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 c28 lcd_de arm_trcdata3 xgpio163 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 b28 lcd_pe arm_trcdata4 xgpio164 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
SPEAR1340 pin description doc id 023063 rev 4 72/200 a28 lcd_r7 arm_trcdata5 xgpio165 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 d27 lcd_r4 arm_trcdata6 xgpio166 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 c27 lcd_r1 arm_trcdata7 xgpio167 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 b27 lcd_vsync arm_trcdata8 xgpio168 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 k28 lcd_pclk arm_trcdata9 xgpio169 (2) o iotype4 pu/ pd 8 ma na io_vdd3v3 i na pu 8ma na 3v3 3v3 cc2 a27 lcd_r6 arm_trcdata10 xgpio170 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 a26 lcd_r3 arm_trcdata11 xgpio171 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 b26 lcd_r0 arm_trcdata12 xgpio172 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 c26 lcd_hsync arm_trcdata13 xgpio173 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
pin description SPEAR1340 73/200 doc id 023063 rev 4 d26 lcd_xr7 arm_trcdata14 xgpio174 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 a25 lcd_xg0 arm_trcdata15 xgpio175 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 b25 lcd_xg1 arm_trcdata16 xgpio176 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 c25 lcd_xg2 arm_trcdata17 xgpio177 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 d25 lcd_led_pwm arm_trcdata18 xgpio178 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 a24 lcd_xg3 arm_trcdata19 xgpio179 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 b24 lcd_xg4 arm_trcdata20 xgpio180 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 c24 lcd_xg5 arm_trcdata21 xgpio181 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 d24 lcd_xg6 arm_trcdata22 xgpio182 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
SPEAR1340 pin description doc id 023063 rev 4 74/200 e24 lcd_xg7 arm_trcdata23 xgpio183 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 a23 lcd_xb0 arm_trcdata24 xgpio184 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 b23 lcd_xb1 arm_trcdata25 xgpio185 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 c23 lcd_xb2 arm_trcdata26 xgpio186 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 d23 lcd_xb3 arm_trcdata27 xgpio187 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 e23 lcd_xb4 arm_trcdata28 xgpio188 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 a22 lcd_xb5 arm_trcdata29 xgpio189 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 b22 lcd_xb6 arm_trcdata30 xgpio190 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 c22 lcd_xb7 arm_trcdata31 xgpio191 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
pin description SPEAR1340 75/200 doc id 023063 rev 4 d22 fsmc_ad25 xgpio192 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 e22 fsmc_ad20 mcif_data15 xgpio193 o io io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 a21 fsmc_ad21 mcif_data14 xgpio194 o io io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 b21 fsmc_ad22 mcif_data13 xgpio195 o io io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 c21 fsmc_ad23 mcif_data12 xgpio196 o io io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 d21 fsmc_ad24 mcif_data11 xgpio197 o io io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 e21 fsmc_ad13 mcif_ncs1 xgpio198 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 a20 fsmc_ad14 mcif_ndmack_nwp xgpio199 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 b20 fsmc_ad15 mcif_data10 xgpio200 o io io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
SPEAR1340 pin description doc id 023063 rev 4 76/200 c20 fsmc_ad18 mcif_data9 xgpio201 o io io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 d20 fsmc_ad19 mcif_data8 xgpio202 o io io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 e20 fsmc_ad8 mcif_niowr_nwe xgpio203 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 a19 fsmc_ad9 mcif_nreset_cf xgpio204 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 b19 fsmc_ad10 mcif_ncs0_nce xgpio205 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 c19 fsmc_ad11 mcif_cf_intr xgpio206 o i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 d19 fsmc_ad12 mcif_iordy xgpio207 o i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 e19 fsmc_ad3 mcif_nce_sd_mmc xgpio208 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 a18 fsmc_ad4 mcif_ncd_cf1 xgpio209 o i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
pin description SPEAR1340 77/200 doc id 023063 rev 4 b18 fsmc_ad5 mcif_ncd_cf2 xgpio210 o i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 c18 fsmc_ad6 mcif_data_dir xgpio211 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 d18 fsmc_ad7 mcif_niord_nre xgpio212 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 e18 mcif_addr0_ale xgpio213 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 a17 mcif_ncd_xd xgpio214 i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 b17 fsmc_ad0 mcif_addr2 xgpio215 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 c17 fsmc_ad1 mcif_nce_cf xgpio216 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 d17 fsmc_ad2 mcif_nce_xd xgpio217 o o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 e17 mcif_sd_cmd xgpio218 io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 a16 mcif_leds xgpio219 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
SPEAR1340 pin description doc id 023063 rev 4 78/200 b16 mcif_data1 xgpio220 io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 c16 mcif_data2 xgpio221 io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 d16 mcif_data3 xgpio222 io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 e16 mcif_data6 xgpio223 io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 b15 mcif_data7 xgpio224 io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 a15 mcif_addr1_cle_clk xgpio225 o io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 c15 mcif_ncd_sd_mmc xgpio226 i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 d15 mcif_dmarq_rnb_wp xgpio227 i io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 e15 mcif_data1_sd xgpio228 io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 a14 mcif_data2_sd xgpio229 io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 b14 mcif_data3_sd xgpio230 io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 c14 mcif_data4 xgpio231 io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
pin description SPEAR1340 79/200 doc id 023063 rev 4 d14 mcif_data5 xgpio232 io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 b10 fsmc_io2 xgpio233 io iotype2 pu/ pd 4/6/8/ 10ma slow /fast io_vdd1v8_3 v3 i na pu 6ma fast 1v8 strap4 cc3 c10 fsmc_io1 xgpio234 io iotype2 pu/ pd 4/6/8/ 10ma slow /fast io_vdd1v8_3 v3 i na pu 6ma fast 1v8 strap4 cc3 d10 fsmc_io0 xgpio235 io iotype2 pu/ pd 4/6/8/ 10ma slow /fast io_vdd1v8_3 v3 i na pu 6ma fast 1v8 strap4 cc3 e10 fsmc_rstpwdwn0 xgpio236 o io iotype2 pu/ pd 4/6/8/ 10ma slow /fast io_vdd1v8_3 v3 i na pu 6ma fast 1v8 strap4 cc3 e14 mcif_data0 xgpio237 io iotype1 pu/ pd 4/6/8/ 10ma slow /fast io_vdd3v3 i na pu 6ma fast 3v3 3v3 cc2 a9 fsmc_io7 xgpio238 io iotype2 pu/ pd 4/6/8/ 10ma slow /fast io_vdd1v8_3 v3 i na pu 6ma fast 1v8 strap4 cc3 b9 fsmc_io6 xgpio239 io iotype2 pu/ pd 4/6/8/ 10ma slow /fast io_vdd1v8_3 v3 i na pu 6ma fast 1v8 strap4 cc3 c9 fsmc_io5 xgpio240 io iotype2 pu/ pd 4/6/8/ 10ma slow /fast io_vdd1v8_3 v3 i na pu 6ma fast 1v8 strap4 cc3 d9 fsmc_io4 xgpio241 io iotype2 pu/ pd 4/6/8/ 10ma slow /fast io_vdd1v8_3 v3 i na pu 6ma fast 1v8 strap4 cc3 e9 fsmc_io3 xgpio242 io iotype2 pu/ pd 4/6/8/ 10ma slow /fast io_vdd1v8_3 v3 i na pu 6ma fast 1v8 strap4 cc3 c8 fsmc_ale_ad17 xgpio243 o io iotype2 pu/ pd 4/6/8/ 10ma slow /fast io_vdd1v8_3 v3 i na pu 6ma fast 1v8 strap4 cc3 table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
SPEAR1340 pin description doc id 023063 rev 4 80/200 d8 fsmc_ren xgpio244 o io iotype2 pu/ pd 4/6/8/ 10ma slow /fast io_vdd1v8_3 v3 i na pu 6ma fast 1v8 strap4 cc3 e8 fsmc_wen xgpio245 o io iotype2 pu/ pd 4/6/8/ 10ma slow /fast io_vdd1v8_3 v3 i na pu 6ma fast 1v8 strap4 cc3 c7 fsmc_rwprt0n xgpio246 o io iotype2 pu/ pd 4/6/8/ 10ma slow /fast io_vdd1v8_3 v3 i na pu 6ma fast 1v8 strap4 cc3 d7 fsmc_rb0 xgpio247 io iotype2 pu/ pd 4/6/8/ 10ma slow /fast io_vdd1v8_3 v3 i na pu 6ma fast 1v8 strap4 cc3 e7 fsmc_cle_ad16 xgpio248 o io iotype2 pu/ pd 4/6/8/ 10ma slow /fast io_vdd1v8_3 v3 i na pu 6ma fast 1v8 strap4 cc3 c6 fsmc_ce0n xgpio249 o io iotype2 pu/ pd 4/6/8/ 10ma slow /fast io_vdd1v8_3 v3 i na pu 6ma fast 1v8 strap4 cc3 c1 rtc_vdd1v5 pwr k13 k17 l10 l12 l14 l16 l18 m11 m17 m19 n10 n12 n18 p11 p17 vdd1v2 pwr table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
pin description SPEAR1340 81/200 doc id 023063 rev 4 r10 r12 r18 t11 t17 t19 u18 v15 v17 v19 w14 w16 w18 m4 vdd1v2 pwr u10 u12 v11 v13 w10 w12 ddrphy_vdd1v2 pwr t6 u5 v6 w5 y6 aa5 ab6 ac7 ac9 ac11 ac13 ad6 ad8 ad10 ddrio_vdd1v8_1v5 pwr table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
SPEAR1340 pin description doc id 023063 rev 4 82/200 ad12 ad14 ddrio_vdd1v8_1v5 pwr c4 adc_avdd2v5 pwr f14 f15 f17 f18 f20 f21 f23 g23 j23 w23 aa23 ac23 ac19 ac17 ac15 u23 io_vdd3v3 pwr f8 f9 io_vdd1v8_3v3 pwr f11 f12 io_vdd1v8_3v3_1 pwr l23 n23 r23 t24 p24 io_vdd2v5_3v3 pwr n2 miphy0_vddpll1v2 pwr table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
pin description SPEAR1340 83/200 doc id 023063 rev 4 p3 miphy0_vdd2pll2v5 pwr l3 miphy0_vddr1v2 pwr n1 miphy0_vddt1v2 pwr e6 pll1_avdd2v5 pwr d6 pll1_vdd1v2 pwr e4 pll2_avdd2v5 pwr d4 pll2_vdd1v2 pwr n5 pll3_avdd2v5 pwr p6 pll3_vdd1v2 pwr ac5 ddr_pll_avdd2v5 pwr u19 otp_vdd2v5 pwr b7 mclk_avdd1v2 pwr b8 mclk_avdd3v3 pwr k4 usb_uhc0_vdd1v2 pwr table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
SPEAR1340 pin description doc id 023063 rev 4 84/200 j4 usb_uhc0_vdd2v5 pwr j3 usb_uhc0_vdd3v3 pwr e2 usb_uhc1_vdd1v2 pwr e3 usb_uhc1_vdd2v5 pwr d3 usb_uhc1_vdd3v3 pwr h4 usb_uoc_vdd1v2 pwr g3 usb_uoc_vdd2v5 pwr g2 usb_uoc_vdd3v3 pwr m6 vreg1_2v5_out o reg out k6 vreg1_3v3_in pwr f6 vreg2_2v5_out o reg out h6 vreg2_3v3_in pwr r5 miphy0_vreg_3v3_in pwr table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
pin description SPEAR1340 85/200 doc id 023063 rev 4 a6 b6 d5 e5 f5 f7 f10 f13 f16 f19 f22 g4 g5 g6 h5 h23 j5 j6 k5 k10 k16 k18 k23 l4 l5 l6 l11 l13 l15 l17 m5 m10 m12 m13 m14 m15 m16 m18 m23 n4 n6 n11 gnd gnd table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
SPEAR1340 pin description doc id 023063 rev 4 86/200 n13 n14 n15 n16 n17 n19 r2 p5 p10 p12 p13 p14 p15 p16 p18 p23 r4 r6 r11 r13 r14 r15 r16 r17 t4 t5 t10 t12 t13 t14 t15 t16 t18 u6 u11 u13 gnd gnd table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
pin description SPEAR1340 87/200 doc id 023063 rev 4 u14 u15 u16 u17 t23 v5 v10 v12 v14 v16 v18 v23 w6 w11 w13 w15 w17 w19 y5 y23 aa6 ab4 ab5 ab23 ac6 ac8 ac10 ac12 ac14 ac16 ac18 ac20 ad7 gnd gnd table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
SPEAR1340 pin description doc id 023063 rev 4 88/200 ad9 ad11 ad13 gnd gnd p4 miphy0_vsspll gnd j1 j2 k3 l1 l2 m3 r3 miphy0_vssr gnd n3 miphy0_vsst gnd h3 usb_vssac gnd c5 adc_agnd gnd a5 adc_vrefp i ana ref b5 adc_vrefn i ana ref ac4 ddrio_vref i ana ref ad5 ddrio_comp_rext io ana ref ac21 io_comp_rext1_3v3 io ana ref ac22 io_comp_gnd1_3v3 gnd ded gnd table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
pin description SPEAR1340 89/200 doc id 023063 rev 4 k19 io_comp_rext2_3v3 io ana ref l19 io_comp_gnd2_3v3 gnd ded gnd k12 io_comp_rext1_1v8_3v 3 io ana ref k11 io_comp_gnd1_1v8_3v3 gnd ded gnd k15 io_comp_rext2_1v8_3v 3 io ana ref k14 io_comp_gnd2_1v8_3v3 gnd ded gnd p19 io_comp_rext_2v5_3v3 io ana ref r19 io_comp_gnd_2v5_3v3 gnd ded gnd r1 miphy0_ref io ana ref g1 usb_txrtune io ana ref 1. this is the input reference clo ck for i2s output functional block. 2. the xgpio169 is the only xgpio pin which is alwa ys an output. all the other xgpio pins are io. table 3. ball characteristics (continued) ball pin name pad type and pad options reset/reset rel. state reset mode reset rel. mode compensation cell signal type pin type pu/ pd drive slew supply name direction out value pu/ pd drive slew
pin description SPEAR1340 90/200 doc id 023063 rev 4 3.3 power supply signals description table 4. power supply signals description pin name description ball signal type pin type adc_agnd adc ground c5 gnd adc_avdd2v5 adc power supply c4 pwr adc_vrefn adc negative voltage reference b5 i ana ref adc_vrefp adc positive voltage reference a5 i ana ref ddr_pll_avdd2v5 ddr pll power supply ac5 pwr ddrio_comp_rext ddr io compensation cell analog reference ad5 io ana ref ddrio_vdd1v8_1v5 ddr io power supply t6 u5 v6 w5 y6 aa5 ab6 ac7 ac9 ac11 ac13 ad6 ad8 ad10 ad12 ad14 pwr ddrio_vref ddr io voltage reference ac4 i ana ref ddrphy_vdd1v2 ddr phy power supply u10 u12 v11 v13 w10 w12 pwr io_comp_gnd_2v5_3v3 iotype3 io compensation cell ground p19 gnd ded gnd io_comp_gnd1_1v8_3v3 iotype2 io compensation cell ground k11 gnd ded gnd io_comp_gnd1_3v3 iotype1 & iotype4 io compensation cell ground ac22 gnd ded gnd io_comp_gnd2_1v8_3v3 iotype2 io compensation cell ground k14 gnd ded gnd io_comp_gnd2_3v3 iotype1 & iotype4 io compensation cell ground l19 gnd ded gnd io_comp_rext_2v5_3v3 iotype3 io compensation cell analog reference r19 io ana ref io_comp_rext1_1v8_3v3 iotype2 io compensation cell analog reference k12 io ana ref io_comp_rext1_3v3 iotype1 & iotype4 io compensation cell analog reference ac21 io ana ref io_comp_rext2_1v8_3v3 iotype2 io compensation cell analog reference k15 io ana ref io_comp_rext2_3v3 iotype1 & iotype4 io compensation cell analog reference k19 io ana ref
SPEAR1340 pin description doc id 023063 rev 4 91/200 io_vdd1v8_3v3 iotype2 io power supply f8 f9 pwr io_vdd1v8_3v3_1 iotype2 io power supply f11 f12 pwr io_vdd2v5_3v3 iotype3 io power supply l23 n23 r23 t24 p24 pwr io_vdd3v3 iotype1 & iotype4 io power supply f14 f15 f17 f18 f20 f21 f23 g23 j23 w23 aa23 ac23 ac19 ac17 ac15 u23 pwr mclk_avdd1v2 master clock oscillator power supply b7 pwr mclk_avdd3v3 master clock oscillator power supply b8 pwr miphy0_ref miphy analog reference r1 io ana ref miphy0_vdd2pll2v5 miphy pll power supply p3 pwr miphy0_vddpll1v2 miphy pll power supply n2 pwr miphy0_vddr1v2 miphy receiver power supply l3 pwr miphy0_vddt1v2 miphy transmitter power supply n1 pwr miphy0_vreg_3v3_in miphy voltage regulator power supply r5 pwr miphy0_vsspll miphy pll ground p4 gnd miphy0_vssr miphy receiver gro und j1 j2 k3 l1 l2 m3 r3 gnd miphy0_vsst miphy transmitter ground n3 gnd otp_vdd2v5 otp antifuses power supply u19 pwr pll1_avdd2v5 pll1 power supply e6 pwr pll1_vdd1v2 pll1 power supply d6 pwr pll2_avdd2v5 pll2 power supply e4 pwr pll2_vdd1v2 pll2 power supply d4 pwr pll3_avdd2v5 pll3 power supply n5 pwr pll3_vdd1v2 pll3 power supply p6 pwr rtc_vdd1v5 real time clock power supply c1 pwr table 4. power supply signals description (continued) pin name description ball signal type pin type
pin description SPEAR1340 92/200 doc id 023063 rev 4 usb_txrtune usb phy analog reference g1 io ana ref usb_uhc0_vdd1v2 usb phy host 0 power supply k4 pwr usb_uhc0_vdd2v5 usb phy host 0 power supply j4 pwr usb_uhc0_vdd3v3 usb phy host 0 power supply j3 pwr usb_uhc1_vdd1v2 usb phy host 1 power supply e2 pwr usb_uhc1_vdd2v5 usb phy host 1 power supply e3 pwr usb_uhc1_vdd3v3 usb phy host 1 power supply d3 pwr usb_uoc_vdd1v2 usb phy otg power supply h4 pwr usb_uoc_vdd2v5 usb phy otg power supply g3 pwr usb_uoc_vdd3v3 usb phy otg power supply g2 pwr usb_vssac usb phy ground h3 gnd vdd1v2 core power supply k13 k17 l10 l12 l14 l16 l18 m11 m17 m19 n10 n12 n18 p11 p17 r10 r12 r18 t11 t17 t19 u18 v15 v17 v19 w14 w16 w18 m4 pwr vreg1_2v5_out voltage regulator 1 output m6 o reg out vreg1_3v3_in voltage regulator 1 power supply k6 pwr vreg2_2v5_out voltage regulator 2 output f6 o reg out table 4. power supply signals description (continued) pin name description ball signal type pin type
SPEAR1340 pin description doc id 023063 rev 4 93/200 vreg2_3v3_in voltage regulator 2 power supply h6 pwr gnd ground a6 b6 d5 e5 f5 f7 f10 f13 f16 f19 f22 g4 g5 g6 h5 h23 j5 j6 k5 k10 k16 k18 k23 l4 l5 l6 l11 l13 l15 l17 m5 m10 m12 m13 m14 m15 m16 m18 m23 n4 n6 n11 n13 n14 n15 n16 n17 n19 r2 p5 p10 p12 p13 p14 p15 p16 p18 p23 r4 r6 r11 r13 r14 r15 r16 r17 t4 t5 t10 t12 t13 t14 t15 t16 t18 u6 u11 u13 u14 u15 u16 u17 t23 v5 v10 v12 v14 v16 v18 v23 w6 w11 w13 w15 w17 w19 y5 y23 aa6 ab4 ab5 ab23 ac6 ac8 ac10 ac12 ac14 ac16 ac18 ac20 ad7 ad9 ad11 ad13 gnd table 4. power supply signals description (continued) pin name description ball signal type pin type
pin description SPEAR1340 94/200 doc id 023063 rev 4 3.4 multiplexed signals description 3.4.1 mac ethernet port multiplexing scheme table 5. mac ethernet port multiplexing scheme ball mac gmii mii rgmii rmii t28 mac_gtxclk125 i - - mac_gtxclk125 i mac_gtxclk125 i r28 mac_gtxclk o - - mac_gtxclk o mac_gtxclk o u28 - - mac_txclk i - - - - u27 mac_txd0 o mac_txd0 o mac_txd0 o mac_txd0 o t26 mac_txd1 o mac_txd1 o mac_txd1 o mac_txd1 o t27 mac_txd2 o mac_txd2 o mac_txd2 o - - t25 mac_txd3 o mac_txd3 o mac_txd3 o - - r25mac_txd4o------ r26mac_txd5o------ p26 mac_txd6 o - - - - - - p27 mac_txd7 o - - - - - - l24 mac_txen o mac_txen o mac_txen o mac_txen o l25 mac_txer o mac_txer o - - - - p28 mac_rxclk i mac_rxclk i mac_rxclk i - - m27 mac_rxdv i mac_rxdv i mac_rxdv i mac_rxdv i m28 mac_rxer i mac_rxer i - - - - r27 mac_rxd0 i mac_rxd0 i mac_rxd0 i mac_rxd0 i r24 mac_rxd1 i mac_rxd1 i mac_rxd1 i mac_rxd1 i p25 mac_rxd2 i mac_rxd2 i mac_rxd2 i - - n24 mac_rxd3 i mac_rxd3 i mac_rxd3 i - - n25mac_rxd4i------ n26mac_rxd5i------ m24mac_rxd6i------ m25mac_rxd7i------ m26 mac_col i mac_col i - - - - l26 mac_crs i mac_crs i - - - - n27 mac_mdc o mac_mdc o mac_mdc o mac_mdc o n28 mac_mdio io mac_mdio io mac_mdio io mac_mdio io
SPEAR1340 pin description doc id 023063 rev 4 95/200 3.4.2 kbd multiplexing scheme 3.4.3 mcif multiplexing scheme table 6. kbd multiplexing scheme ball signal name gpio keyboard 6x6 keyboard 2x2 a11 kbd_row5 kbd_row5 keyboard output (row5) e12 kbd_row4 kbd_row4 keyboard output (row4) d12 kbd_row3 kbd_row3 keyboard output (row3) c12 kbd_row2 kbd_row2 keyboard output (row2) b12 kbd_row1 kbd_row1 keyboard output (row1) keyboard output (row1) a12 kbd_row0 kbd_row0 keyboard output (row0) keyboard output (row0) ae18 kbd_col5 kbd_col5 keyboard input (col5) a10 kbd_col4 kbd_col4 keyboard input (col4) e11 kbd_col3 kbd_col3 keyboard input (col3) d11 kbd_col2 kbd_col2 keyboard input (col2) c11 kbd_col1 kbd_col1 keyboard input (col1) keyboard input (col1) b11 kbd_col0 kbd_col0 keyboard input (col0) keyboard input (col0) table 7. mcif multiplexing scheme ball signal name asynchronous card synchronous card compact flash xd card sd/sdio/mmc e14 mcif_data0 mcif_data0 io mcif_data0 io mcif_data0 io b16 mcif_data1 mcif_data1 io mcif_data1 io - - c16 mcif_data2 mcif_data2 io mcif_data2 io - - d16 mcif_data3 mcif_data3 io mcif_data3 io - - c14 mcif_data4 mcif_data4 io mcif_data4 io mcif_data4 io d14 mcif_data5 mcif_data5 io mcif_data5 io mcif_data5 io e16 mcif_data6 mcif_data6 io mcif_data6 io mcif_data6 io b15 mcif_data7 mcif_data7 io mcif_data7 io mcif_data7 io e15 mcif_data1_sd - - - - mcif_data1_sd io a14 mcif_data2_sd - - - - mcif_data2_sd io b14 mcif_data3_sd - - - - mcif_data3_sd io
pin description SPEAR1340 96/200 doc id 023063 rev 4 d21 mcif_data8 mcif_data8 io - - - - c21 mcif_data9 mcif_data9 io - - - - b21 mcif_data10 mcif_data10 io - - - - a21 mcif_data11 mcif_data11 io - - - - e22 mcif_data12 mcif_data12 io - - - - e15 mcif_data13 mcif_data13 io - - - - a14 mcif_data14 mcif_data14 io - - - - b14 mcif_data15 mcif_data15 io - - - - e18 mcif_addr0_ale mcif_addr0_ale o mcif_addr0_ale o - - a15 mcif_addr1_cle_ clk mcif_addr1_cle_ clk o mcif_addr1_cle_ clk o mcif_addr1_cle_ clk o b17 mcif_addr2 mcif_addr2 o - - - - c17 mcif_nce_cf mcif_nce_cf o - - - - d17 mcif_nce_xd - - mcif_nce_xd o - e19 mcif_nce_sd_mm c ---- mcif_nce_sd_mm c o a18 mcif_ncd_cf1 mcif_ncd_cf1 i - - - - b18 mcif_ncd_cf2 mcif_ncd_cf2 i - - - - a17 mcif_ncd_xd mcif_ncd_xd i - - c15 mcif_ncd_sd_mm c ---- mcif_ncd_sd_mm c i c18 mcif_data_dir mcif_data_dir o mcif_data_dir o mcif_data_dir o d15 mcif_dmarq_rnb_ wp mcif_dmarq_rnb _wp i mcif_dmarq_rnb _wp i mcif_dmarq_rnb _wp i d18 mcif_niord_nre mcif_ni ord_nre o mcif_niord_nre o - - e20 mcif_niowr_nwe mcif_niow r_nwe o mcif_niowr_nwe o - - a19 mcif_nreset_cf mcif_nreset_cf o - - - b19 mcif_ncs0_nce mcif_ncs0_nce o mcif_ncs0_nce o - - c19 mcif_cf_intr mcif_cf_intr i - - - d19 mcif_iordy mcif_iordy i - - - e21 mcif_ncs1 mcif_ncs1 o - - - - a20 mcif_ndmack_nw p mcif_ndmack_nw p o mcif_ndmack_nw p o- - e17 mcif_sd_cmd - - - - mcif_sd_cmd io a16 mcif_leds mcif_leds o mcif_leds o mcif_leds o table 7. mcif multiplexing scheme (continued) ball signal name asynchronous card synchronous card compact flash xd card sd/sdio/mmc
SPEAR1340 pin description doc id 023063 rev 4 97/200 3.4.4 fsmc multiplexing scheme table 8. fsmc multiplexing scheme ball signal name nand nor asynchronous sram d10 fsmc_io0 fsmc_io0 io fsmc_io0 io fsmc_io0 io c10 fsmc_io1 fsmc_io1 io fsmc_io1 io fsmc_io1 io b10 fsmc_io2 fsmc_io2 io fsmc_io2 io fsmc_io2 io e9 fsmc_io3 fsmc_io3 io fsmc_io3 io fsmc_io3 io d9 fsmc_io4 fsmc_io4 io fsmc_io4 io fsmc_io4 io c9 fsmc_io5 fsmc_io5 io fsmc_io5 io fsmc_io5 io b9 fsmc_io6 fsmc_io6 io fsmc_io6 io fsmc_io6 io a9 fsmc_io7 fsmc_io7 io fsmc_io7 io fsmc_io7 io a12 fsmc_io8 fsmc_io8 io fsmc_io8 io fsmc_io8 io b12 fsmc_io9 fsmc_io9 io fsmc_io9 io fsmc_io9 io c12 fsmc_io10 fsmc_io10 io fsmc_io10 io fsmc_io10 io d12 fsmc_io11 fsmc_io11 io fsmc_io11 io fsmc_io11 io e12 fsmc_io12 fsmc_io12 io fsmc_io12 io fsmc_io12 io a11 fsmc_io13 fsmc_io13 io fsmc_io13 io fsmc_io13 io b11 fsmc_io14 fsmc_io14 io fsmc_io14 io fsmc_io14 io c11 fsmc_io15 fsmc_io15 io fsmc_io15 io fsmc_io15 io c6 fsmc_ce0n fsmc_ce0n o fsmc_ce0n o fsmc_ce0n o e8 fsmc_wen fsmc_wen o fsmc_wen o fsmc_wen o d8 fsmc_ren fsmc_ren o fsmc_ren o fsmc_ren o c8 fsmc_ale_ad17 fsmc_ale_ad17 o f smc_ale_ad17 o fsmc_ale_ad17 o e7 fsmc_cle_ad16 fsmc_cle_ad16 o f smc_cle_ad16 o fsmc_cle_ad16 o d7 fsmc_rb0 fsmc_rb0 i fsmc_av o fsmc_bl0n o c7 fsmc_rwprt0n fsmc_rwprt0n o fsmc_rwprt0n o fsmc_bl1n o b17 fsmc_ad0 fsmc_ad0 o fsmc_ad0 o c17 fsmc_ad1 fsmc_ad1 o fsmc_ad1 o d17 fsmc_ad2 fsmc_ad2 o fsmc_ad2 o e19 fsmc_ad3 fsmc_ad3 o fsmc_ad3 o a18 fsmc_ad4 fsmc_ad4 o fsmc_ad4 o b18 fsmc_ad5 fsmc_ad5 o fsmc_ad5 o c18 fsmc_ad6 fsmc_ad6 o fsmc_ad6 o d18 fsmc_ad7 fsmc_ad7 o fsmc_ad7 o e20 fsmc_ad8 fsmc_ad8 o fsmc_ad8 o a19 fsmc_ad9 fsmc_ad9 o fsmc_ad9 o
pin description SPEAR1340 98/200 doc id 023063 rev 4 b19 fsmc_ad10 fsmc_ad10 o fsmc_ad10 o c19 fsmc_ad11 fsmc_ad11 o fsmc_ad11 o d19 fsmc_ad12 fsmc_ad12 o fsmc_ad12 o e21 fsmc_ad13 fsmc_ad13 o fsmc_ad13 o a20 fsmc_ad14 fsmc_ad14 o fsmc_ad14 o b20 fsmc_ad15 fsmc_ad15 o fsmc_ad15 o c20 fsmc_ad18 fsmc_ad18 o fsmc_ad18 o d20 fsmc_ad19 fsmc_ad19 o fsmc_ad19 o e22 fsmc_ad20 fsmc_ad20 o fsmc_ad20 o a21 fsmc_ad21 fsmc_ad21 o fsmc_ad21 o b21 fsmc_ad22 fsmc_ad22 o fsmc_ad22 o c21 fsmc_ad23 fsmc_ad23 o fsmc_ad23 o d21 fsmc_ad24 fsmc_ad24 o fsmc_ad24 o d22 fsmc_ad25 fsmc_ad25 o fsmc_ad25 o d11 fsmc_ce1n fsmc_ce1n o fsmc_ce1n o fsmc_ce1n o e11 fsmc_rwprt1n fsmc_rwprt1n o fsmc_rwprt1n o e10 fsmc_rstpwdn0 fsmc_rstpwdn0 o a10 fsmc_rstpwdn1 fsmc_rb1 i fsmc_rstpwdn1 o table 8. fsmc multiplexing scheme (continued) ball signal name nand nor asynchronous sram
SPEAR1340 pin description doc id 023063 rev 4 99/200 3.5 signals description 3.5.1 cpu subsystem table 9. cpu subsystem - a9sm signals description signal name description type ball arm_trstn jtag reset i ae15 arm_tck jtag clock i ad16 arm_tms jtag mode select i ae16 arm_tdi jtag data input i ad15 arm_tdo jtag data output io af16 arm_trcclk trace clock o e27 arm_trcctl trace control o e26 arm_trcdata0 trace data o e25 arm_trcdata1 d28 arm_trcdata2 f24 arm_trcdata3 c28 arm_trcdata4 b28 arm_trcdata5 a28 arm_trcdata6 d27 arm_trcdata7 c27 arm_trcdata8 b27 arm_trcdata9 k28 arm_trcdata10 a27 arm_trcdata11 a26 arm_trcdata12 b26 arm_trcdata13 c26 arm_trcdata14 d26 arm_trcdata15 a25 arm_trcdata16 b25 arm_trcdata17 c25 arm_trcdata18 d25 arm_trcdata19 a24 arm_trcdata20 b24 arm_trcdata21 c24 arm_trcdata22 d24 arm_trcdata23 e24
pin description SPEAR1340 100/200 doc id 023063 rev 4 3.5.2 memories arm_trcdata24 trace data o a23 arm_trcdata25 b23 arm_trcdata26 c23 arm_trcdata27 d23 arm_trcdata28 e23 arm_trcdata29 a22 arm_trcdata30 b22 arm_trcdata31 c22 table 9. cpu subsystem - a9sm signals description (continued) signal name description type ball table 10. memories - mpmc signals description signal name description type ball ddr2n_ddr3 this pin is used to select the ddr2 or ddr3 operation mode for ddr2/3 buffers. 0 ddr2 selection 1 ddr3 selection iaf14 ddr_addr0 memory address bus o u3 ddr_addr1 w2 ddr_addr2 v2 ddr_addr3 v3 ddr_addr4 y2 ddr_addr5 w1 ddr_addr6 y4 ddr_addr7 v1 ddr_addr8 t1 ddr_addr9 u4 ddr_addr10 aa3 ddr_addr11 v4 ddr_addr12 aa2 ddr_addr13 y1 ddr_addr14 w4 ddr_rasn memory row address select (active low) o ad3 ddr_casn memory columns address select (active low) o ad4 ddr_wen memory write transfer cycle (active low) o aa4 ddr_cs0n memory chip select 0 (active low) o ab3
SPEAR1340 pin description doc id 023063 rev 4 101/200 ddr_cs1n memory chip select 1 (active low) o u1 ddr_ba0 memory bank address o y3 ddr_ba1 w3 ddr_ba2 aa1 ddr_cke memory clock enable (active high) o t3 ddr_odt0 memory odt signal o ac3 ddr_odt1 u2 ddr_dm0 memory data mask (active high) o ae5 ddr_dm1 ag3 ddr_dm2 af10 ddr_dm3 ag8 ddr_dqs0p differential memory data strobe active high; drove during write transaction and received from memory device during read during transfer io ae3 ddr_dqs1p ah4 ddr_dqs2p ae9 ddr_dqs3p ah10 ddr_dqs0n differential memory data strobe active low; drove during write transaction and received from memory device during read during transfer io af3 ddr_dqs1n ag4 ddr_dqs2n af8 ddr_dqs3n ag9 ddr_dq0 memory data bus io af2 ddr_dq1 af4 ddr_dq2 af1 ddr_dq3 af5 ddr_dq4 ae1 ddr_dq5 ae6 ddr_dq6 ae2 ddr_dq7 ae4 ddr_dq8 ah3 ddr_dq9 ah2 ddr_dq10 ah6 ddr_dq11 ag1 ddr_dq12 ag5 ddr_dq13 ag2 table 10. memories - mpmc signals description (continued) signal name description type ball
pin description SPEAR1340 102/200 doc id 023063 rev 4 ddr_dq14 memory data bus io ah5 ddr_dq15 ah1 ddr_dq16 ae8 ddr_dq17 ae10 ddr_dq18 af7 ddr_dq19 ae11 ddr_dq20 ae7 ddr_dq21 af11 ddr_dq22 af6 ddr_dq23 af9 ddr_dq24 ah9 ddr_dq25 ah8 ddr_dq26 ag11 ddr_dq27 ag6 ddr_dq28 ag10 ddr_dq29 ah7 ddr_dq30 ah11 ddr_dq31 ag7 ddr_resetn memory reset (active low) o t2 ddr_clkm0 differential memory clock (active low) o ad2 ddr_clkm1 ac2 ddr_clkm2 ab2 ddr_clkp0 differential memory clock (active high) o ad ddr_clkp1 ac1 ddr_clkp2 ab1 table 10. memories - mpmc signals description (continued) signal name description type ball
SPEAR1340 pin description doc id 023063 rev 4 103/200 table 11. memories - fsmc signals description signal name description type ball fsmc_io0 data bus io d10 fsmc_io1 c10 fsmc_io2 b10 fsmc_io3 e9 fsmc_io4 d9 fsmc_io5 c9 fsmc_io6 b9 fsmc_io7 a9 fsmc_io8 a12 fsmc_io9 b12 fsmc_io10 c12 fsmc_io11 d12 fsmc_io12 e12 fsmc_io13 a11 fsmc_io14 b11 fsmc_io15 c11 fsmc_ad0 address bus o b17 fsmc_ad1 c17 fsmc_ad2 d17 fsmc_ad3 e19 fsmc_ad4 a18 fsmc_ad5 b18 fsmc_ad6 c18 fsmc_ad7 d18 fsmc_ad8 e20 fsmc_ad9 a19 fsmc_ad10 b19 fsmc_ad11 c19 fsmc_ad12 d19 fsmc_ad13 e21 fsmc_ad14 a20 fsmc_ad15 b20 fsmc_ad18 c20 fsmc_ad19 d20 fsmc_ad20 e22
pin description SPEAR1340 104/200 doc id 023063 rev 4 fsmc_ad21 address bus o a21 fsmc_ad22 b21 fsmc_ad23 c21 fsmc_ad24 d21 fsmc_ad25 d22 fsmc_ce0n (1) nand/nor/sram chip select (default nand) o c6 fsmc_ce1n d11 fsmc_wen write enable o e8 fsmc_ren read enable o d8 fsmc_ale_ad17 address latch enable /address pin #17 o c8 fsmc_cle_ad16 command latch enable / address pin #16 o e7 fsmc_rb0 nand ready/busy[0] or nor address valid or sram byte lane[0] (valid only for 16-bit configuration) io d7 fsmc_rstpwdwn1 nand ready/busy[1] or nor reset power down[1] io a10 fsmc_rwprt0n nand/nor write protect [0] or sram byte lane[1] (valid only for 16-bit configuration) o c7 fsmc_rwprt1n nand/nor write protect [1] e11 fsmc_rstpwdwn0 nor reset / power down [0] o e10 1. fsmc_ce0n is used for booting fr om parallel nor or nand flash. table 11. memories - fsmc signals description (continued) signal name description type ball table 12. memories - smi signals description signal name description type ball smi_datain data in from ex ternal serial flash i ab25 smi_dataout data out to external serial flash o ab24 smi_clk data out clock to external flash o ab28 smi_cs0n (1) chip selects (active low) o aa27 smi_cs1n ab26 1. smi_cs0n is used for booting from serial nor.
SPEAR1340 pin description doc id 023063 rev 4 105/200 3.5.3 clocks and resets 3.5.4 debug interface note: 1 the arm trace ports are enabled via the miscellaneous registers. 2 for arm jtag mode, the test[4:0] pins should be set to ?00001? at power-up. for functional mode, the same pins should be set to ?00000?. 3 when the 2v5 power supply is not present on the otp supply ball, the jtag debug features are not available on the device. table 13. main clock and reset pins descriptions signal name description type ball mclk_xi master clock (mclk) 24 mhz (typical) crystal in osc a7 mclk_xo master clock (mclk) 24 mhz (typical) crystal out a8 rtc_xi real-time clock (rtc) 32 khz crystal in osc b1 rtc_xo real-time clock (r tc) 32 khz crystal out a1 mresetn main reset iotyp e1 af15 table 14. debug pins description signal name description type ball arm_trstn test reset input i ae15 arm_tck test trace clock i ad16 arm_tdi test trace data input i ad15 arm_tms test trace mode select i ae16 arm_tdo test trace data output io af16
pin description SPEAR1340 106/200 doc id 023063 rev 4 3.5.5 connectivity table 15. connectivity - mac phy interface signals description signal name description type ball mac_gtxclk125 auxiliary source of clock i t28 mac_gtxclk transmission clock this is the transmission clock provided by the external phy/oscillator/internal pll for the rgmii,gmii, rmii. all the rgmii,gmii, rmii transmission signals generated by the mac are synchronous to this clock. rmii: this clock is used also as receive clock, so all the receive signals are synchronous to this clock. or28 mac_txclk transmission clock this is the transmission clock (25/2. 5 mhz in 100m/10mbps) provided by the external phy for the mii. all the mii transmission signals generated by the mac are synchronous to this clock. iu28 mac_txd0 phy transmit data this is a bundle of eight transmit data signals driven by the mac. it has multiple functions depending on which ph y interface is selected, as given below. unused bits in the rgmii,rmii,mi i interface configurations are tied to low. ? gmii: all 8 bits provide the gmii transmit data byte. the validity of the data is qualified with mac_txen and mac_txer. note: using 10/100 mbps-only operation, mac_txd bus is only 4 bits wide (mac_txd[3:0]). ? mii: bits [3:0] provide the mii transm it data nibble. the validity of the data is qualified with mac_txen and mac_txer. ? rgmii: bits [3:0] provide the rg mii transmit data. the data bus changes with both rising and falling edges of the transmit clock. the validity of the data is qualified with mac_txen. ? rmii: bits [1:0] provide the rmii trans mit data. the validity of the data is qualified with mac_txen. o u27 mac_txd1 t26 mac_txd2 t27 mac_txd3 t25 mac_txd4 r25 mac_txd5 r26 mac_txd6 p26 mac_txd7 p27 mac_txen phy transmit data enable this signal is driven by the mac and has multiple functions depending on which phy interface is selected, as given below. ? gmii/mii/rmii: when high, indicates th at valid data is being transmitted on the mac_txd bus. ? rgmii: this signal is the control signal for the transmit data, and is driven on both edges of the clock. o l24 mac_txer phy transmit error this signal is driven by the mac and has multiple functions depending on which phy interface is selected, as given below. ? gmii/mii: when high, indicates a trans mit error or carrier extension (in gmii) on the mac_txd bus. ? rmii, rgmii: not used. tied low in some configurations; driven low in others. o l25
SPEAR1340 pin description doc id 023063 rev 4 107/200 mac_rxclk reception clock (rmii_clk) this is the reception clock (125/25/2.5 mhz in 1g/100m/10mbps) provided by the external phy for rgmii,gmii,mii. all the rgmii,gmii,mii receive signals received by the mac are synchronous to this clock. ip28 mac_rxdv phy receive data valid this signal is driven by phy and has multiple functions depending on which phy interface is selected as given below. ? gmii/mii: when high, indicates that data on the mac_rxd bus is valid. it remains asserted continuously from the first recovered byte/nibble of the frame through the final recovered byte/nibble. ? rgmii: this is the receive control signal used to qualify the data received on mac_rxd bus. this signal is sampled on both edges of the clock. ? rmii: contains the crs and data valid information of the receive interface. im27 mac_rxer phy receive error this signal is driven by the phy and has multiple functions depending on which phy interface is selected as given below. ? gmii/mii: when high, indicates an error or carrier extension (in gmii) in the received frame on the mac_rxd bus. ? rgmii/rmii: not used. im28 mac_rxd0 phy receive data this is a bundle of eight data signals received from the phy. it has multiple functions depending on which phy interface is selected, as given below. ? gmii: all 8 bits provide the gmii receive data byte. the validity of the data is qualified with mac_rxdv and mac_rxer. note: using 10/100 mbps-only operation, mac_rxd bus is only 4 bits wide (mac_rxd[3:0]). ? mii: bits [3:0] provide the mii receive data nibble. the validity of the data is qualified with mac_rxdv and mac_rxer. ? rgmii: bits [3:0] provide the rgmii receive data. the data bus is sampled with both rising and falling edges of the receive clock (mac_rxclk). the validity of the data is qualified with mac_rxdv. ? rmii: bits [1:0] provide the rmii receive data. the validity of the data is qualified with mac_rxdv. i r27 mac_rxd1 r24 mac_rxd2 p25 mac_rxd3 n24 mac_rxd4 n25 mac_rxd5 n26 mac_rxd6 m24 mac_rxd7 m25 mac_col phy collision this signal, valid only in gmii/mii mode, is asserted by the phy when a collision is detected on the medium. this signal is not synchronous to any clock.(active high) im26 mac_crs phy crs this signal, valid only in gmii/mii mode, is asserted by the phy when either the transmit or receive medium is not idle. the phy deasserts this signal when both transmit and receive medium are idle. this signal is not synchronous to any clock. (active high) i l26 table 15. connectivity - mac phy interface signals description (continued) signal name description type ball
pin description SPEAR1340 108/200 doc id 023063 rev 4 mac_mdc management data clock the mac provides timing reference fo r the mac_mdio sig nal through this aperiodic clock. the maximum frequency of this clock is 2.5 mhz.this clock is generated from the application clock (hclk) via a clock divider. on27 mac_mdio management data input/output. io n28 table 15. connectivity - mac phy interface signals description (continued) signal name description type ball table 16. connectivity - pcie/sata physical interface (miphy) signals description (1) signal name description type ball miphy single lane miphy0_txp positive tx output o m2 miphy0_txn negative tx output o m1 miphy0_rxp positive rx input i k2 miphy0_rxn negative rx input i k1 miphy0_xtal1 input of the crystal oscillator ip2 miphy0_xtal2 io p1 1. pcie and sata cannot be used simultaneously; one port in alternative to the other one. to select between pcie or sata you have to configure the register pcie_sata_cfg[0], pcie_sata_sel. table 17. connectivity - usb 2.0 host signals description signal name description type ball usb_uhc0_drvvbus usb host 0 vbus, port power switch o b13 usb_uhc1_drvvbus usb host 1 vbus, port power switch o c13 usb_uhc0_overcur port overcurrent indication from application id13 usb_uhc1_overcur ie13 table 18. connectivity - usb 2.0 otg signals description signal name description type ball usb_uoc_drvvbus power switch to 5 v charge pump o a13
SPEAR1340 pin description doc id 023063 rev 4 109/200 table 19. connectivity - usb 2.0 phy signals description signal name description type ball usb_uhc0_dp usb host 0 d+ io h1 usb_uhc0_dm usb host 0 d- io h2 usb_uhc1_dp usb host 1 d+ io d1 usb_uhc1_dm usb host 1 d- io d2 usb_uoc_dp usb otg d+ io f1 usb_uoc_dm usb otg d- io f2 usb_uoc_id usb otg mini-receptacle identifier i f4 usb_uoc_vbus usb otg power supply pin: ? when spear is configur ed as usb device, this is a vbus detect signal. ? when spear is configured as usb ho st, this is a power supply pin. a charge pump external to the usb phy must provide power to this pin (and to pin1 of the micro-u sb connector). the nominal voltage for this pin is 5 v. the voltage range is 0-5.25 v. io f3 table 20. connectivity - uart signals description signal name description type ball uart0 uart0_rxd uart0 receive serial data input irda input (sirin) iy25 uart0_txd uart0 transmitted serial data output irda output (sirout) oy24 uart0_rtsn uart0 request to send modem status output (active low) o af17 uart0_ctsn uart0 clear to send modem status input (active low) i af18 uart0_dcdn uart0 data carrier detect modem status input (active low) i ag18 uart0_dtrn uart0 data terminal ready modem status output (active low) o ae17 uart0_dsrn uart0 data set ready modem status input (active low) i ah17 uart0_rin uart0 ring indicator mode m status input (active low) i ag17 uart1 uart1_rxd uart1 receive serial data input irda input (sirin) iy27 uart1_txd uart1 transmitted serial data output irda output (sirout) oy26
pin description SPEAR1340 110/200 doc id 023063 rev 4 table 21. connectivity - ssp signals d escription signal name description type ball ssp_sck ssp clock. it is used as output in master mode as input in slave mode io aa26 ssp_miso master input slave output io aa25 ssp_mosi master output slave input io aa24 ssp_ss0n ssp frame output (master mode), input (slave mode) io ab27 ssp_ss1n slave select 1 (used only in master mode) o ae19 ssp_ss2n slave select 2 (used only in master mode) o aa28 ssp_ss3n slave select 3 (used only in master mode) o l27 table 22. connectivity - i2c signals description signal name description type ball i2c0 i2c0_sda i2c0 input/output data iod k27 i2c0_scl i2c0 input/output clock iod l28 i2c1 i2c1_sda i2c1 input/output data iod ah18 i2c1_scl i2c1 input/output clock iod ah19 table 23. connectivity- mcif signals description signal name description (1) type ball mcif_data0 all modes data0 line io e14 mcif_data1 compact flash (cf)/xd card: data lines (3 to 1) io b16 mcif_data2 io c16 mcif_data3 io d16 mcif_data4 mmc8/cf/xd card: data lines (7 to 4) io c14 mcif_data5 io d14 mcif_data6 io e16 mcif_data7 io b15
SPEAR1340 pin description doc id 023063 rev 4 111/200 mcif_data8 compact flash (cf): data lines (15 to 8) io d20 mcif_data9 io c20 mcif_data10 io b20 mcif_data11 io d21 mcif_data12 io c21 mcif_data13 io b21 mcif_data14 io a21 mcif_data15 io e22 mcif_data1_sd sd/sdio/mmc: data lines (3 to 1) io e15 mcif_data2_sd io a14 mcif_data3_sd io b14 mcif_addr0_ale cf: a0 address bit 0, used to select one of the eight registers in the task file xd: address latch enable oe18 mcif_addr1_cle_clk cf: a1 address bit 1, used to select one of the eight registers in the task file xd: command latch enable sd: sd/sdio/mmc clock oa15 mcif_addr2 cf: a2 address bit 2, used to select one of the eight registers in the task file ob17 mcif_nce_cf cf: chip enable (active low) oc17 mcif_nce_xd xd: chip enable (active low) od17 mcif_nce_sd_mmc sd: chip enable (active low) oe19 mcif_ncd_cf1 cf: -cd1, -cd2 these card detect pins are connected to ground on the cf storage card or cf+ card. they are used by the host to determine that the cf storage card or cf+ card is fully inserted into its socket ia18 mcif_ncd_cf2 ib18 mcif_ncd_xd xd: card insert/remove pin: 0 - card inserted 1 - card removed ia17 mcif_ncd_sd_mmc sd: card detection for single slot, active low ic15 mcif_data_dir all modes data direction on board oc18 table 23. connectivity- mcif signals description (continued) signal name description (1) type ball
pin description SPEAR1340 112/200 doc id 023063 rev 4 mcif_dmarq_rnb_wp cf: dmarq a dma request, asserted by the device when it is ready to transfer data to or from the host. for multiword dma transfers, the direction of data transfer is controlled by -iord and -iowr. the device waits until the host asserts -dmack before negating dmarq, and then reasserts dmarq if there is more data to transfer. dmarq is not driven when the device is not selected. while a dma operation is in progress, -cs0 and ?cs1 are held negated. xd: ready/busy output from xd card. sd: active high. sd card write protect id15 mcif_niord_nre cf: -iord, -hdmardy, hstrobe. an io read strobe (-iord) generated by the host. this signal gates io data onto the bus from the cf storage card or cf+ card when the card is configured to use the interface. when in ultra dma mode, dma read is active; this signal (- hdmardy) is asserted by the host to indicate that the host is read to receive ultra dma data-in bursts . the host may negate -hdmardy to pause an ultra dma transfer. when ub ultra dma mode, dma write is active; this signal is the data out strobe (hstrobe) generated by the host. both the rising and falling edge of hstrobe cause data to be latched by the device. the host may stop generating hstrobe edges to pause an ultra dma dataout burst. xd: read enable od18 mcif_niowr_nwe cf: -iowr, stop the io write strobe (-iowr) pulse is used to clock io data on the card data bus into the cf+ card controller register s when the cf+ card is configured to use the io interface. the clocking occurs on the negative to positive (trailing) edge of the signal. while ultra dma mode protocol is active, the assertion of this signal (stop) causes the termination of the ultra dma burst. this signal must be negated before entering ultra dma mode protocol. xd write enable oe20 mcif_nreset_cf cf: -reset active low hardware reset from the host oa19 mcif_ncs0_nce cf: -cs0 -cs0 is the chip select for the task file registers. while -dmack is asserted, this signal is held negated. xd: chip enable ob19 mcif_cf_intr cf: intrq active high interrupt request from the device to the host ic19 table 23. connectivity- mcif signals description (continued) signal name description (1) type ball
SPEAR1340 pin description doc id 023063 rev 4 113/200 mcif_iordy cf: iordy, -ddmardy, dstrobe except in ultra dma mode, this input signal may be used as iordy. when in ultra dma mode, dma write is active; this signal (- ddmardy) is asserted by the device to indicate that the device is read to receive ultra dma data-in bursts. the device may negate - ddmardy to pause an ultra dma transfer. when ultra dma mode dma read is active, this signal is the data out strobe (dstrobe) generated by the device. both the rising and falling edge of dstrobe cause data to be latched by the host. the device may stop generating dstrobe edges to pause an ultra dma data-out burst id19 mcif_ncs1 cf: -cs1 -cs1 is used to select the alternate status register and the device control register. while -dmack is asserted, this signal is held negated oe21 mcif_ndmack_nwp cf: -dmack a dma acknowledge signal that is asserted by the host in response to dmarq to initiate dma transfers. when dma operations are not active, the card ignores the -dmack signal, including a floating condition. xd: write protect oa20 mcif_sd_cmd sd: command /response line io e17 mcif_leds all modes monitors bus activity when data transfer occurs. caution : do not remove the card while it is being accessed oa16 1. for more details on the use of each signal, please refer to table 7: mcif multiplexing scheme . table 23. connectivity- mcif signals description (continued) signal name description (1) type ball table 24. connectivity - kbd signals description signal name signal type description ball keyboard gpio keyboard gpio kbd_row5 od io strobe 5, active low gpio. input/output a11 kbd_row4 od io strobe 4, active low e12 kbd_row3 od io strobe 3, active low d12 kbd_row2 od io strobe 2, active low c12 kbd_row1 od io strobe 1, active low b12 kbd_row0 od io strobe 0, active low a12 kbd_col5 i io pressed key5, active low ae18 kbd_col4 i io pressed key4, active low a10
pin description SPEAR1340 114/200 doc id 023063 rev 4 3.5.6 audio kbd_col3 i io pressed key3, active low gpio. input/output e11 kbd_col2 i io pressed key2, active low d11 kbd_col1 i io pressed key1, active low c11 kbd_col0 i io pressed key0, active low b11 table 24. connectivity - kbd si gnals descripti on (continued) signal name signal type description ball keyboard gpio keyboard gpio table 25. connectivity - cec signals description signal name description type ball cec0 cec0 cec0 rx/tx data io k25 cec1 cec1 cec1 rx/tx data io k24 table 26. audio - i2s signals description signal name description type ball i2sin i2s_in_data3 data input for receive mode iy28 i2s_in_data2 iw24 i2s_in_data1 iw25 i2s_in_data0 iw26 i2s_in_ws word select line for receive mode i v24 i2s_in_bitclk serial interface clock i w28 i2sout i2s_out_data3 data output for transmit mode ou25 i2s_out_data2 ov25 i2s_out_data1 ou26 i2s_out_data0 ov26 i2s_out_ws word select line for transmit mode - (active high) o u24 i2s_out_bitclk serial interface clock o w27 i2s_out_refclk input reference clock for i2s output functional block (audio crystal) i v27 i2s_out_ovrsamp_clk oversampling/reference clock for external audio devices o v28
SPEAR1340 pin description doc id 023063 rev 4 115/200 3.5.7 video table 27. audio - s/pdif signals description signal name description type ball spdif_in s/pdif input i ad17 spdif_out s/pdif output o k26 table 28. video - lcd controller signals description signal name description type ball lcd_r0 port 1 red data o b26 lcd_r1 c27 lcd_r2 f24 lcd_r3 a26 lcd_r4 d27 lcd_r5 d28 lcd_r6 a27 lcd_r7 a28 lcd_g0 port 1 green data o e25 lcd_g1 e28 lcd_g2 g24 lcd_g3 h24 lcd_g4 f25 lcd_g5 g25 lcd_g6 f26 lcd_g7 g26 lcd_b0 port 1 blue data o h26 lcd_b1 h25 lcd_b2 j25 lcd_b3 j26 lcd_b4 j27 lcd_b5 j28 lcd_b6 j24 lcd_b7 h27
pin description SPEAR1340 116/200 doc id 023063 rev 4 lcd_xr0 port 2 red data o e26 lcd_xr1 f27 lcd_xr2 g27 lcd_xr3 e27 lcd_xr4 f28 lcd_xr5 g28 lcd_xr6 h28 lcd_xr7 d26 lcd_xg0 port 2 green data o a25 lcd_xg1 b25 lcd_xg2 c25 lcd_xg3 a24 lcd_xg4 b24 lcd_xg5 c24 lcd_xg6 d24 lcd_xg7 e24 lcd_xb0 port 2 blue data o a23 lcd_xb1 b23 lcd_xb2 c23 lcd_xb3 d23 lcd_xb4 e23 lcd_xb5 a22 lcd_xb6 b22 lcd_xb7 c22 lcd_pclk pixel clock to lcd panel o k28 lcd_hsync horizontal sync pulse o c26 lcd_vsync vertical sync pulse o b27 lcd_de data enable o c28 lcd_led_pwm lcd led pulse width modulation o d25 lcd_pe power enable o b28 table 28. video - lcd controller signals description (continued) signal name description type ball
SPEAR1340 pin description doc id 023063 rev 4 117/200 table 29. video - vip signals description signal name description type ball vip_r0 red data i ah26 vip_r1 ae24 vip_r2 ag23 vip_r3 ah22 vip_r4 af22 vip_r5 af23 vip_r6 af24 vip_r7 ae25 vip_r8 af26 vip_r9 af27 vip_r10 red data i ad24 vip_r11 ac24 vip_r12 ac28 vip_r13 ad27 vip_r14 ae28 vip_r15 ag28 vip_g0 green data i ah28 vip_g1 ae26 vip_g2 ad26 vip_g3 ac26 vip_g4 ac25 vip_g5 ad25 vip_g6 af28 vip_g7 ah27 vip_g8 ag26 vip_g9 ah25 vip_g10 ah23 vip_g11 ag22 vip_g12 ah21 vip_g13 ag21 vip_g14 af21 vip_g15 ae21
pin description SPEAR1340 118/200 doc id 023063 rev 4 vip_b0 blue data i af25 vip_b1 ag24 vip_b2 ae23 vip_b3 ae22 vip_b4 ad22 vip_b5 ad23 vip_b6 ah24 vip_b7 ag25 vip_b8 ad21 vip_b9 ag20 vip_b10 ah20 vip_b11 ad19 vip_b12 ad20 vip_b13 blue data i ae20 vip_b14 af20 vip_b15 ad18 vip_pixclk pixel clock from vip panel i ad28 vip_hsync horizontal sync pulse i ac27 vip_vsync vertical sync pulse i ae27 vip_de data enable i ag27 table 29. video - vip signals description (continued) signal name description type ball table 30. video - cam signals description signal name description type ball cam1 cam1_data0 cam1 data i ad26 cam1_data1 ac25 cam1_data2 ad25 cam1_data3 ac24 cam1_data4 ad24 cam1_data5 ac28 cam1_data6 ad27 cam1_data7 ae28 cam1_pixclk pixel clock from cam1 panel iad28 cam1_vsync cam1 vertical sync pulse iac26
SPEAR1340 pin description doc id 023063 rev 4 119/200 cam1_hsync cam1 horizontal sync pulse i ac27 cam2 cam2_data0 cam2 data i ah28 cam2_data1 ae26 cam2_data2 af28 cam2_data3 ah27 cam2_data4 af27 cam2_data5 af26 cam2_data6 ag28 cam2_data7 ag26 cam2_pixclk pixel clock from cam2 panel iah26 cam2_vsync cam2 vertical sync pulse i ae27 cam2_hsync cam2 horizontal sync pulse i ag27 cam3 cam3_data0 cam3 data i af24 cam3_data1 ae25 cam3_data2 af25 cam3_data3 cam3 data ag24 cam3_data4 ag25 cam3_data5 ah24 cam3_data6 ah25 cam3_data7 ah23 cam3_pixclk pixel clock from cam3 panel iah22 cam3_vsync cam3 vertical sync pulse i ae24 cam3_hsync cam3 horizontal sync pulse i ag23 cam4 cam4_data0 cam4 data i ad20 cam4_data1 ae20 cam4_data2 af20 cam4_data3 ag20 cam4_data4 ag21 cam4_data5 af21 cam4_data6 ae21 cam4_data7 ad21 table 30. video - cam signals description (continued) signal name description type ball
pin description SPEAR1340 120/200 doc id 023063 rev 4 3.5.8 timers 3.5.9 miscellaneous cam4_pixclk pixel clock from cam4 panel iah20 cam4_vsync cam4 vertical sync pulse iad18 cam4_hsync cam4 horizontal sync pulse i ad19 table 30. video - cam signals description (continued) signal name description type ball table 31. gpt signals description signal name description type ball gpt0 gpt0_tmr_cpt1 asynchronous signal provided for the measurement of timing signals in timer 1 iaf19 gpt0_tmr_clk1 this clock toggles each time the timer 1 interrupt goes active. o af18 gpt0_tmr_cpt2 asynchronous signal provided for the measurement of timing signals in timer 2 iag17 gpt0_tmr_clk2 this clock toggles each time the timer 2 interrupt goes active. o ag19 gpt1 gpt1_tmr_cpt1 asynchronous signal provided for the measurement of timing signals in timer 1 i ae17 gpt1_tmr_clk1 this clock toggles each time the timer 1 interrupt goes active. o ah17 gpt1_tmr_cpt2 asynchronous signal provided for the measurement of timing signals in timer 2 iaf17 gpt1_tmr_clk2 this clock toggles each time the timer 2 interrupt goes active. o ag18 table 32. miscellaneous - adc signals description signal name description type ball ain0 analog inputs #(0..7) ia4 ain1 ib4 ain2 ic3 ain3 ia3 ain4 ia2 ain5 ib2 ain6 ib3 ain7 ic2 touch_xy_sel touchscreen select o aa28
SPEAR1340 pin description doc id 023063 rev 4 121/200 table 33. miscellaneous - pwm signals description signal name description type ball pwm1 channel 1 o ae19 pwm2 channel 2 o ae18 pwm3 channel 3 o af19 pwm4 channel 4 o ag19 table 34. miscellaneous - gpio signals description signal name description type ball gpio_a0 io data io d11 gpio_a1 io e11 gpio_a2 io a10 gpio_a3 io af17 gpio_a4 io ag17 gpio_a5 io ah17 gpio_a6 io ae17 gpio_a7 io ag18 gpio_b0 io af18 gpio_b1 io ae18 gpio_b2 io ah18 gpio_b3 io ad17 gpio_b4 io ad18 gpio_b5 io af19 gpio_b6 io ag19 gpio_b7 io ah19 table 35. pcm signals description signal name description type ball gpio_wkup_trig wake-up trigger from gpio i ae18 ddrphy_vdd1v2_off controls the (optional) external (i.e. board) power switch on the ddrphy 1v2 supply line. oaf19 ddrio_vdd1v8_1v5_off controls the (optional) external (i.e. board) power switch on the ddrphy 1v5/1v8 supply line. oag19
pin description SPEAR1340 122/200 doc id 023063 rev 4 table 36. xgpio signals description signal name description type ball xgpio0 general purpose io io a12 xgpio1 io b12 xgpio2 io c12 xgpio3 io d12 xgpio4 io e12 xgpio5 io a11 xgpio6 io b11 xgpio7 io c11
SPEAR1340 pin description doc id 023063 rev 4 123/200 xgpio24 general purpose io io ae19 xgpio25 io ah20 xgpio26 io ad19 xgpio27 io ad20 xgpio28 io ae20 xgpio29 io af20 xgpio30 io ag20 xgpio31 io ad21 xgpio32 io ae21 xgpio33 io af21 xgpio34 io ag21 xgpio35 io ah21 xgpio36 io ad22 xgpio37 io ae22 xgpio38 io af22 xgpio39 io ah22 xgpio40 io ag22 xgpio41 io ad23 xgpio42 io ae23 xgpio43 io af23 xgpio44 io ag23 xgpio45 io ah23 xgpio46 io ah24 xgpio47 io ag24 xgpio48 io af24 xgpio49 io ae24 xgpio50 io ah25 xgpio51 io ag25 xgpio52 io af25 xgpio53 io ae25 xgpio54 io ah26 xgpio55 io ag26 xgpio56 io af26 xgpio57 io ah27 xgpio58 io ah28 table 36. xgpio signals description (continued) signal name description type ball
pin description SPEAR1340 124/200 doc id 023063 rev 4 xgpio59 general purpose io io ag27 xgpio60 io ag28 xgpio61 io af27 xgpio62 io af28 xgpio63 io ae26 xgpio64 io ae27 xgpio65 io ae28 xgpio66 io ad24 xgpio67 io ad25 xgpio68 io ad26 xgpio69 io ad28 xgpio70 io ad27 xgpio71 io ac24 xgpio72 io ac25 xgpio73 io ac26 xgpio74 io ac27 xgpio75 io ac28 xgpio76 io ab24 xgpio77 io ab25 xgpio78 io ab28 xgpio79 io ab26 xgpio80 io ab27 xgpio81 io aa24 xgpio82 io aa25 xgpio83 io aa26 xgpio84 io aa27 xgpio85 io aa28 xgpio86 io y24 xgpio87 io y25 xgpio88 io y26 xgpio89 io y27 xgpio90 io y28 xgpio91 io w24 xgpio92 io w25 xgpio93 io w26 table 36. xgpio signals description (continued) signal name description type ball
SPEAR1340 pin description doc id 023063 rev 4 125/200 xgpio94 general purpose io io v24 xgpio95 io v25 xgpio96 io v26 xgpio97 io w27 xgpio98 io u24 xgpio99 io w28 xgpio100 io u25 xgpio101 io u26 xgpio102 io v27 xgpio103 io v28 xgpio104 io u28 xgpio105 io u27 xgpio106 io t26 xgpio107 io t27 xgpio108 io t28 xgpio109 io t25 xgpio110 io r25 xgpio111 io r26 xgpio112 io r27 xgpio113 io r28 xgpio114 io r24 xgpio115 io p26 xgpio116 io p27 xgpio117 io p28 xgpio118 io p25 xgpio119 io n24 xgpio120 io n25 xgpio121 io n26 xgpio122 io n27 xgpio123 io n28 xgpio124 io m24 xgpio125 io m25 xgpio126 io m26 xgpio127 io m27 xgpio128 io m28 table 36. xgpio signals description (continued) signal name description type ball
pin description SPEAR1340 126/200 doc id 023063 rev 4 xgpio129 general purpose io io l24 xgpio130 io l25 xgpio131 io l26 xgpio132 io l27 xgpio133 io k27 xgpio134 io l28 xgpio135 io k25 xgpio136 io k24 xgpio137 io k26 xgpio138 io j24 xgpio139 io j28 xgpio140 io j27 xgpio141 io j26 xgpio142 io j25 xgpio143 io h28 xgpio144 io h27 xgpio145 io h26 xgpio146 io h25 xgpio147 io h24 xgpio148 io g28 xgpio149 io g27 xgpio150 io g26 xgpio151 io g25 xgpio152 io g24 xgpio153 io f28 xgpio154 io f27 xgpio155 io f26 xgpio156 io f25 xgpio157 io e28 xgpio158 io e27 xgpio159 io e26 xgpio160 io e25 xgpio161 io d28 xgpio162 io f24 xgpio163 io c28 table 36. xgpio signals description (continued) signal name description type ball
SPEAR1340 pin description doc id 023063 rev 4 127/200 xgpio164 general purpose io io b28 xgpio165 io a28 xgpio166 io d27 xgpio167 io c27 xgpio168 io b27 xgpio169 ok28 xgpio170 io a27 xgpio171 io a26 xgpio172 io b26 xgpio173 io c26 xgpio174 io d26 xgpio175 io a25 xgpio176 io b25 xgpio177 io c25 xgpio178 io d25 xgpio179 io a24 xgpio180 io b24 xgpio181 io c24 xgpio182 io d24 xgpio183 io e24 xgpio184 io a23 xgpio185 io b23 xgpio186 io c23 xgpio187 io d23 xgpio188 io e23 xgpio189 io a22 xgpio190 io b22 xgpio191 io c22 xgpio192 io d22 xgpio193 io e22 xgpio194 io a21 xgpio195 io b21 xgpio196 io c21 xgpio197 io d21 xgpio198 io e21 table 36. xgpio signals description (continued) signal name description type ball
pin description SPEAR1340 128/200 doc id 023063 rev 4 xgpio199 general purpose io io a20 xgpio200 io b20 xgpio201 io c20 xgpio202 io d20 xgpio203 io e20 xgpio204 io a19 xgpio205 io b19 xgpio206 io c19 xgpio207 io d19 xgpio208 io e19 xgpio209 io a18 xgpio210 io b18 xgpio211 io c18 xgpio212 io d18 xgpio213 io e18 xgpio214 io a17 xgpio215 io b17 xgpio216 io c17 xgpio217 io d17 xgpio218 io e17 xgpio219 io a16 xgpio220 io b16 xgpio221 io c16 xgpio222 io d16 xgpio223 io e16 xgpio224 io b15 xgpio225 io a15 xgpio226 io c15 xgpio227 io d15 xgpio228 io e15 xgpio229 io a14 xgpio230 io b14 xgpio231 io c14 xgpio232 io d14 xgpio233 io b10 table 36. xgpio signals description (continued) signal name description type ball
SPEAR1340 pin description doc id 023063 rev 4 129/200 xgpio234 general purpose io io c10 xgpio235 io d10 xgpio236 io e10 xgpio237 io e14 xgpio238 io a9 xgpio239 io b9 xgpio240 io c9 xgpio241 io d9 xgpio242 io e9 xgpio243 io c8 xgpio244 io d8 xgpio245 io e8 xgpio246 io c7 xgpio247 io d7 xgpio248 io e7 xgpio249 io c6 table 36. xgpio signals description (continued) signal name description type ball
pin description SPEAR1340 130/200 doc id 023063 rev 4 3.6 strapping options the following two tables show the strappin g options available (s trap[6:0]) on SPEAR1340. strap[6:0] pins are sampled at reset release and they are reusable after the internal latching for different purposes. when used as output pins, these pins require no special conditions, but when used as input pins, the application must keep them in a non-driving (tri- state) mode for at least 2 s after mresetn is released. strap[6:0] pins are sampled by internal hardware logic during the power-on reset sequence and latched on the bootstrap_cfg register in the misc. table 37. strapping options signal name description type ball strap0 the bootrom firmware selects the booting device after reset release by reading the status of the strap[3:0] pins. s ae19 strap1 sah20 strap2 sad19 strap3 sad20 strap4 used to select the usage of nand flash 8-bit interface working as 3v3 or 1v8, along with ce0n: strap4= 1 --> 3v3 strap4= 0 --> 1v8 s ae20 strap5 used to select the usage of nand flash extension to 16-bit interface and/or second chip select ce1n working as 3v3 or 1v8: strap5= 1 --> 3v3 strap5= 0 --> 1v8 saf20 strap6 used to select the gmii/rgmii interface working at 3v3 or 2v5: strap6= 1 --> 2v5 strap6= 0 --> 3v3 sag20 table 38. hardware boot selection (strap[0..3]) primary source backup source (1) strap3 strap2 strap1 strap0 bypass na 0 0 0 0 serial nor flash (2) usb otg (device) 0001 nand flash (3) usb otg (device) 0010 parallel nor flash (8-bit) (3) usb otg (device) 0011 parallel nor flash (16-bit) (3) usb otg (device) 0100 uart na 0101 rfu (4) na 0110 rfu na 0 1 1 1 usb otg (device) na 1 0 0 0 serial nor flash (2) uart 1001 nand flash (3) uart 1010
SPEAR1340 pin description doc id 023063 rev 4 131/200 parallel nor flash (8-bit) (3) uart 1011 parallel nor flash (16-bit) (3) uart 1100 mmc/sd memory card na 1 1 0 1 rfu na 1 1 1 0 rfu na 1 1 1 1 1. the backup source will be used in case that the primary source is not available. 2. to boot from serial nor flash use smi_cs0n. 3. to boot from nand flash or pa rallel nor flash use fsmc_ce0n. 4. reserved for future use. table 38. hardware boot selection (strap[0..3]) (continued) primary source backup source (1) strap3 strap2 strap1 strap0
electrical characteristics SPEAR1340 132/200 doc id 023063 rev 4 4 electrical characteristics this chapter provides the electrical characteristics for SPEAR1340. please refer to an3317, application notes, pcb guidelines for SPEAR1340 for additional details. 4.1 absolute maximum ratings SPEAR1340 contains devices to protect the inputs against dama ge due to high/low static voltages. however, it is advisable to take normal precaution to avoid application of any voltage higher/lower than the specified maximum/minimum rated voltages. caution: stresses above those listed in ta bl e 3 9 and table 40 may cause permanent damage to the device. exposure to maximum rating conditio ns for extended periods may affect device reliability. table 39. voltage absolute maximum ratings symbol parameter min max unit v dd 1v2 1v2 power supply -0.3 1.44 v v dd 2v5 2v5 power supply -0.3 3 v dd 3v3 3v3 power supply -0.3 3.9 v dd rtc rtc 1v5 power supply -0.3 2.16 v dd ddr ddr2 1v8 power supply -0.3 2.16 ddr3 1v5 power supply -0.3 2.16 v dd 1v8/3v3 programmable 1v8 power supply -0.3 3.9 programmable 3v3 power supply -0.3 3.9 v dd 2v5/3v3 programmable 2v5 power supply -0.3 3.9 programmable 3v3 power supply -0.3 3.9 table 40. thermal absolute maximum ratings symbol parameter min max unit t stg storage temperature range -55 150 c t j junction temperature -40 125
SPEAR1340 electrical characteristics doc id 023063 rev 4 133/200 4.2 recommended operating conditions to ensure proper operation of the device, it is highly recommended to follow the conditions shown in ta b l e 41 . table 41. recommended operating conditions symbol parameter ball min typ max unit v dd 1v2 1v2 power supply k13 k17 l10 l12 l14 l16 l18 m11 m17 m19 n10 n12 n18 p11 p17 r10 r12 r18 t11 t17 t19 u18 v15 v17 v19 w14 w16 w18 m4 u10 u12 v11 v13 w10 w12 n2 l3 n1 d6 d4 p6 k4 e2 h4 1.14 1.2 1.3 v v dd 2v5 2v5 power supply c4, p3, e6, e4, n5, ac5, u19, j4, e3, g3 2.25 2.5 2.75 v v dd 3v3 3v3 power supply f14 f15 f17 f18 f20 f21 f23 g23 j23 w23 aa23 ac23 ac19 ac17 ac15 u23 b8 j3 d3 g2 k6 h6 r5 3.0 3.3 3.6 v v dd rtc rtc 1v5 power supply c1 1.3 1.5 1.8 v v dd ddr ddr2 1v8 power supply t6 u5 v6 w5 y6 aa5 ab6 ac7 ac9 ac11 ac13 ad6 ad8 ad10 ad12 ad14 1.7 1.8 1.9 v ddr3 1v5 power supply 1.4 1.5 1.6 v v dd 1v8/3v3 programmable 1v8 power supply f8 f9 f11 f12 1.65 1.8 1.95 v programmable 3v3 power supply 3.0 3.3 3.6 v v dd 2v5/3v3 programmable 2v5 power supply l23 n23 r23 t24 p24 2.25 2.5 2.75 v programmable 3v3 power supply 3.0 3.3 3.6 v t c case temperature ? -40 85 c
electrical characteristics SPEAR1340 134/200 doc id 023063 rev 4 4.3 clocking parameters 4.3.1 master clock (mclk) external clock generated from a crystal oscillator figure 7. mclk crystal connection 1. cl1 and cl2 are the load capacitors. the value of the capacitors depends on the type of the selected crystal. to calculate the value of the load capacitance, use the formula given below. for this example, aker c2e-24.000-12-3030-x 24 mhz oscillator has been used. formula c l c l1 c l2 u c l1 c l2 + -------------------------- c s + = where cl1 and cl2 are the load capacitors an d cs is the circuit stray capacitance. in our application: cl1 cl 2 cext table 42. mclk oscillator characteristics symbol parameter conditions min typ max unit f osc_in oscillator frequency 24 (1) 1. a frequency of 24 mhz is mandatory to obtain the r equired frequencies for all clocks generated by the pll of the usb phy. 33 (2) 2. at max freq = 33 mhz the esr value has to be less than 20 : mhz esr equivalent series resisistance 50 : gm oscillator transconductance startup 19.8 28.5 ma/v t su startup time stabilized power on mclk_avdd3v3 pin 2 (3) 3. startup time simulated with a 30 mhz crystal. ms v dd 3v3 24 mhz cl1 cl2 (1) (1) mclk_xi mclk_xo
SPEAR1340 electrical characteristics doc id 023063 rev 4 135/200 this implies: cext = (cl-cs)*2 example: for the aker c2e-24.000-12-3030-x crystal, cl = 12 pf with cs = 3 pf, we have: cext = cl1 = cl2 = 18 pf mclk generated from an external clock source table 43. mclk external user clock source characteristics symbol parameter conditions min typ max unit f mclk_xi external clock source frequency no limitation 24 (1) 33 mhz v mclk_xih mclk_xi input pin high level voltage mclk_avdd3v3 - 0.3 mclk_avdd3v3 v v mclk_xil mclk_xi input pin low level voltage mclk_gndsub 0.3 v ducy (mclk_xi) duty cycle (2) 40 60 % t r(mclk_xi) t f(mclk_xi) mclk_xi input rise and fall time -5% of the clock period +5% of the clock period % c in(mclk_xi) mclk_xi input capacitance 7pf i l(mclk_xi) mclk_xi input leakage current mclk_gndsub v in mclk_avdd3v3 1a 1. a frequency of 24 mhz is mandatory to obtai n the required operating frequency for all clocks generated by the pll from the usb phy. 2. an initial delay of 1 s + 2048 f mclk_xi cycles occurs for duty cycle detecti on and internal clock availability.
electrical characteristics SPEAR1340 136/200 doc id 023063 rev 4 4.3.2 real-time clock (rtc) external clock generated from a crystal oscillator figure 8. rtc crystal connection 1. cl1 and cl2 are the load capacitors. the value of the capacitors depends on the type of the selected crystal. to calculate the value of the load capacitance, use the formula given below. formula c l c l1 c l2 u c l1 c l2 + -------------------------- c s + = where c l1 and c l2 are the load capacitors and c s is the circuit stray capacitance. in our application: c l1 = c l2 = c ext this implies: c ext = (c l -c s )*2 table 44. rtc oscillator characteristics symbol parameter condition min typ max unit f osc_in oscillator frequency 32.768 khz esr equivalent series resistance 6000 : gm oscillator transconductance startup 12 25 a/v t su startup time stabilized power on rtc_vdd1v5 pin 1.5 f osc_in cycles gn d 32.768 khz cl1 cl2 (1) (1) rtc_xi rtc_xo
SPEAR1340 electrical characteristics doc id 023063 rev 4 137/200 example: for this example, a fox electronics, nc26l f-327 32.768 khz osc illator has been used. for the fox electronics, nc26lf-327 crystal, c l = 12.5 pf with c s = ~0.1 pf, we have: cext = c l1 = cl2 = 24.8 pf=22 pf rtc clock generated from an external clock source table 45. rtc external user clock source characteristics symbol parameter condition min typ max unit f rtc_xi external clock source frequency 32.768 khz v rtc_xih rtc_xi input pin high level voltage rtc_vdd1v5 - 0.2 rtc_vdd1v5 v v rtc_xil rtc_xi input pin low level voltage rtc_gnd 0.2 v ducy (rtc_xi) duty cycle 40 60 % t r(rtc_xi) tf (rtc_xi) rtc_xi input rise and fall time 50 ns c in(rtc_xi) rtc_xi input capacitance 5pf i l(rtc_xi) rtc_xi input leakage rtc_gnd v in rtc_vdd1v5 1a
electrical characteristics SPEAR1340 138/200 doc id 023063 rev 4 4.4 i/o ac/dc characteristics the following sections show the electrical ac/dc characteristics of the i/os present in SPEAR1340. 4.4.1 3v3/2v5/1v8 i/o buffer s (iotype1/iotype2/iotype3) the 3v3/2v5/1v8 buffers are designed to operate at 3.3 v, 2 . 5 v, and 1.8 v supply level. even if they support switchable supplies, ea ch i/o type has limited supply flexibility by design: iotype1: only 3v3 iotype2: 3v3/1v8 iotype3: 3v3/2v5 features switchable 1.8 v, 2.5 v, or 3.3 v supply input with hysteresis programmable drive and slew programmable pull-up/down functionality dc characteristics ta bl e 46 shows the dc characteristics for 3v3/2v5/1v8 i/o buffers. table 46. 3v3/2v5/1v8 i/o dc characteristics symbol parameter conditions min typ max unit vddx 1v8 supply voltage ? 1.65 ? 1.95 v 2v5 supply voltage ? 2.25 ? 2.75 v 3v3 supply voltage ? 3.0 ? 3.6 v receiver characteristics (1) 1v8 i/o operation v ih high level input voltage ? 0.65*vdd x ? vddx+0.3 v v il low level input voltage ? -0.3 ? 0.35*vdd x v v hyst schmitt trigger hysteresis ? 50 ? - mv 2v5 i/o operation v ih high level input voltage ? 1.7 ? vddx+0.3 v v il low level input voltage ? -0.3 ? 0.7 v v hyst schmitt trigger hysteresis ? 50 ? mv 3v3 i/o operation v ih high level input voltage ? 2.0 ? vddx+0.3 v
SPEAR1340 electrical characteristics doc id 023063 rev 4 139/200 v il low level input voltage ? -0.3 ? 0.8 v v hyst schmitt trigger hysteresis - 50 - mv pull-up and pull-down characteristics 1v8 i/o operation r pu (50 k ? ) equivalent pull-up resistance vi= 0v 50 - k r pd equivalent pull-down resistance vi= vddx 50 - - k 2v5 i/o operation r pu (50 k ? ) equivalent pull-up resistance vi= 0v 50 - k r pd equivalent pull-down resistance vi= vddx 50 - - k 3v3 i/o operation r pu (50k ? ) equivalent pull-up resistance vi= 0v 50 - k r pd equivalent pull-down resistance vi= vddx 50 - - k output characteristics 1v8 i/o operation v ol low level output voltage i ol (2) =4 /6 /8 /10 ma - - 0.4 v v oh high level output voltage i oh = 4 /6 /8 /10 ma vddx-0.4 - - v 2v5 i/o operation v ol low level output voltage i ol = 4 /6 /8 /10 ma - - 0.4 v v oh high level output voltage i oh = 4 /6 /8 /10 ma vddx-0.4 - - v 3v3 i/o operation v ol low level output voltage i ol = 4 /6 /8 /10 ma - - 0.4 v v oh high level output voltage i oh = 4 /6 /8 /10 ma vddx-0.4 - - v 1. external drivers must be powered at the sa me voltage as the relative spear input pad. 2. at v ol /v oh level, i ol /i oh is the minimum source/sink current drive, w hen the buffer is programme d at corresponding drive level by core drive select pins. table 46. 3v3/2v5/1v8 i/o dc characteristics (continued) symbol parameter conditions min typ max unit
electrical characteristics SPEAR1340 140/200 doc id 023063 rev 4 ac characteristics ta bl e 47 and ta bl e 48 show the ac input and output characteristics for 3v3/2v5/1v8 i/o buffers. table 47. 3v3/2v5/1v8 i/o ac input characteristics max frequency max load comment 1v8 i/o operation 200 mhz 1 pf this load is placed at zi. (see figure 9 below) 2v5/3v3 i/o operation 200 mhz 1 pf this load is placed at zi. table 48. 3v3/2v5/1v8 i/o ac output characteristics drive fast slew nominal slew frequency (mhz) load (pf) frequency (mhz) load (pf) 1v8 i/o operation 4 ma 20 20 8 20 40 6 16 6 6 ma 30 20 12 20 60 6 24 6 8 ma 40 20 16 20 80 6 32 6 10 ma 50 20 20 20 100 6 40 6 2v5/3v3 i/o operation 4 ma 30 20 12 20 60 6 24 6 6 ma 45 20 18 20 90 6 36 6 8 ma 60 20 24 20 120 6 48 6 10 ma 70 20 28 20 140 6 56 6
SPEAR1340 electrical characteristics doc id 023063 rev 4 141/200 figure 9. 3v3/2v5/1v8 i/o input test setup figure 10. 3v3/2v5/1v8 i/o output test setup io p a d zi c z a io p a d c l c p l p
electrical characteristics SPEAR1340 142/200 doc id 023063 rev 4 4.4.2 iotype4 i/o buffers there is only one i/o pin of this type: xgpio169 (ball k28). features 3.3 v signaling programmable pull-up/down functionality dc characteristics ta bl e 49 shows the dc characteristics of iotype4 buffers. table 49. iotype4 dc characteristics symbol parameter conditions min typ max unit v dd 3v3 supply voltage - 3.0 - 3.6 v receiver characteristics (1) 1. external drivers must be powered at the sa me voltage as the relative spear input pad. v ih high level input voltage -2.0-v dd 3v3+0.5 v v il low level input voltage --0.5-0.8v driver characteristics i oh source current v oh = v dd 3v3-0.2 8 - - ma i ol sink current v ol = 0.2 8 - - ma pull-up and pull-down characteristics r pu equivalent pull-up resistance v pad = 0 - 50 - k r pd equivalent pull-down resistance v pad = v dd 3v3 - 50 - k
SPEAR1340 electrical characteristics doc id 023063 rev 4 143/200 ac characteristics ta bl e 50 shows the ac characteristics of iotype4 buffers. figure 11. iotype4 input test setup figure 12. iotype4 output test setup 1. parasitic capacitance and inductance are not shown her e, but taken into account with measurement setup. for values of l and c, please refer to table 49: iotype4 dc characteristics . table 50. input (i/o) pin capacitance symbol parameter conditions min typ max unit receiver characteristics c z capacitive load at zi ? ? ? 1 pf duty cycle duty cycle at zi (1) 1. with input duty cycle of 50% at i/o. 45 ? 55 % driver characteristics c l capacitive load at i/o ? ? ? 40 pf frequency operating frequency (2) 2. output swing from 2.4v to 0.4 v is guaranteed for this operating frequency range. ? ? 100 mhz duty cycle duty cycle at i/o (3) 3. with input duty cycle of 50% at a. 45 ? 55 % io p a d zi c z a io p a d c l
electrical characteristics SPEAR1340 144/200 doc id 023063 rev 4 4.4.3 ddr2 and ddr3 mode i/o buffers this section is applicable to i/o pins of type sstl (sstl 1v5/1v8). the ddr2/ddr3 buffers can work either with 1.8 v supply in ddr2 applications or 1.5 v in ddr3 applications. features 1.5 v and 1.8 v signaling pseudo-differential input for data and fully-differential input for strobe. on-die termination (odt) functi onality, in order to integrate the parallel resistor inside the die and improve signal integrity. ac/dc characteristics ta bl e 51 shows the ac/dc characteristics of ddr2 and ddr3 buffers. table 51. ddr2/ddr3 ac/dc driver characteristics symbol parameter conditions min typ max unit v dd ddr ddr2 1v8 supply voltage - 1.7 1.8 1.9 v ddr3 1v5 supply voltage - 1.4 1.5 1.6 v z out output impedance vpad= v dd ddr/2 r ext = 332 mandatory 34.3-10% = 30.9 34.3 34.3 + 10% = 37.7 v oh (ac) high level output voltage - ddr2: v dd ddr/2 + 0.2 --v ddr3: v dd ddr/2 + 0.175 v ol (ac) low level output voltage -- - ddr2: v dd ddr/2-02 v - ddr3: v dd ddr/2- 0.175 v oh (dc) high level output voltage - ddr2: v dd ddr/2 + 0.125 --v ddr3: v dd ddr/2 + 0.1 v ol (dc) low level output voltage -- - ddr2: v dd ddr/2 - 0.125 v - ddr3: v dd ddr/2 - 0.1
SPEAR1340 electrical characteristics doc id 023063 rev 4 145/200 to measure rt1 or rt2: r tx v ih dc () v il dc () ? iv ih dc () () iv il dc () () ? ------------------------------------------------------------ - = 1. apply v ih (dc) and v il (dc) to the iopad pin separately while the i/o is in input mode with the odt enabled. 2. measure the current i(v ih (dc)) and i(v il (dc)) according to the following equation: to measure deltavm: deltav m 2v m u v dd ddr ? v dd ddr ------------------------------------------------ - ?1 100 u = 1. measure voltage at the iopad pin while the i/o is in input mode with the odt enabled. 2. calculate deltav m according to the following equation: table 52. ddr2/ddr3 pseudo-differential receiver ac and dc characteristics symbol parameter ddr2 ddr3 unit min typ max min typ max v dd ddr ddr2/ddr3 supply voltage 1.71.81.91.41.51.6v v ref voltage reference 0.49 * v dd ddr 0.5 * v dd ddr 0.51 * v dd ddr 0.49 * v dd ddr 0.5 * v dd ddr 0.51 * v dd ddr v v ih (ac) high level input voltage (1) - (1) v ref + 0.1 - (1) v v il (ac) low level input voltage - (1) -v ref - 0.1 v v ih (dc) high level input voltage - 0.8 * v dd ddr - (1) v v il (dc) low level input voltage - (1) - 0.2 * v dd ddr v 1. no data available in jedec update. table 53. ddr2/ddr3 on-die terminati on (odt) dc characteristics symbol parameter min typ max unit r t1 ( ddr2) lower effective impedance value for ddr2 60 75 90 : r t2 ( ddr2) higher effective impedance value for ddr2 120 150 180 : r t1 (ddr3) lower effective impedance value for ddr3 53 (60-12%) 60 69 (60+15%) : r t2 ( ddr3) higher effective impedance value for ddr3 106 (120-12%) 120 138 (120+15%) : deltav m deviation of v m with respect to v dd ddr/2 -5 - 1 %
electrical characteristics SPEAR1340 146/200 doc id 023063 rev 4 4.5 voltage regulator characteristics SPEAR1340 has three inter nal voltage regulators: miphy single-lane regulator: the voltage co ntrolled by this regulator is internally connected to the miphy supply, but it is also externally visible on miphy0_vdd2pll2v5. the regulator is always active; it is not possible to bypass it. vreg1 regulator: used only for usb vreg2 regulator: used for all plls (pll1, pll2, pll3, ddr pll), adc and otp. each regulator receives a 3v3 voltage supply as input and generates a 2v5 voltage supply as output. the following table shows the main requirements for the voltage regulators. 4.6 miphy characteristics for sata operation, the miphy0_xtal1/miphy0_xtal2 clock input can be implemented by a 25 mhz crystal oscillator. for pcie operation, a suitable clock driver such as on semiconductor nb3n 5573 or silicon labs si533 0c_a000207 can be used. table 54. voltage regulators requirements voltage regulator input v oltage regulator output balls connected input voltage output voltage max current external capacitor miphy0_vreg_3v3_in miphy0_vdd2pll2v5 p3 3.3 v 2.5 v 100 ma 10 f vreg1_3v3_in vreg1_2v5_out (ball m6) j4 e3 g3 3.3 v 2.5 v 150 ma 2.2 f vreg2_3v3_in vreg2_2v5_out (ball f6) e6 e4 n5 ac5 u19 c4 3.3 v 2.5 v 150 ma 2.2 f table 55. miphy characteristics symbol parameter min typ max unit f osc miphy0_xtal1/miphy0_xtal2 clock input frequency for sata configuration 25 mhz miphy0_xtal1/miphy0_xtal2 clock input frequency for pcie configuration 100 v ih miphy0_rxp/miphy0_rxn differential input high voltage +150 mv v il miphy0_rxp/miphy0_rxn differential input low voltage -150 mv v in(osc) miphy0_xtal1/miphy0_xtal2 clock input voltage -0.3 1.15 v z in(osc) miphy0_xtal1/miphy0_xtal2 clock input impedance 50
SPEAR1340 electrical characteristics doc id 023063 rev 4 147/200 4.7 required external components some pads require the use of an external resistor. ta b l e 56 lists these pads and the value of the resistors to be used. table 56. list of required resistors pad name value ball miphy0_ref 487 ( 1%) r1 usb_txrtune 43.2 ( 1%) g1 ddrio_comp_rext 332 ( 1%) ad5 io_comp_rext1_3v3 121 k ( 1%) ac21 io_comp_rext2_3v3 121 k ( 1%) k19 io_comp_rext1_1v8_3v3 121 k ( 1%) k12 io_comp_rext2_1v8_3v3 121 k ( 1%) k15 io_comp_rext_2v5_3v3 121 k ( 1%) r19
electrical characteristics SPEAR1340 148/200 doc id 023063 rev 4 4.8 power-up sequence it is recommended to power up the power supplies in the order shown in figure 13 . v dd 1v2 is brought up first, followed by v dd 1v5/1v8, and then v dd 3v3. the minimum time ( t) between each power up is >0 s. note: the 2v5 power supply is generated by internal voltage regulators, just after the 3v3. make sure that different 2v5 inpu t power rails are driven by spear internal regulators. figure 13. power-up sequence 4.9 power-down sequence all power supplies can be shut down at the same time. v dd 1v2 v dd v dd 3 v3 power-up sequence t t t 1v5/1v 8
SPEAR1340 electrical characteristics doc id 023063 rev 4 149/200 4.10 reset release the master reset (m resetn) must be released after a ll the power supplies are stable and for a time interval of 2 ms, which is the start-up time of the main oscillator, and must be asserted low for at least 1 s for warm reset. figure 14. cold reset release figure 15. warm reset release note: see also: section 5.1: reset timing characteristics on page 151 . 4.11 adc electrical characteristics v dd 1v2 v dd v dd 3 v 3 1v5/1v 8 mre s etn trp(cold)= 2 m s trp(w a rm)= 500 ns mre s etn table 57. adc characteristics symbol parameters min typ max unit f adc_clk adc_clk frequency 2.5 14 20 mhz av dd adc supply voltage 2.25 2.5 2.75 v v refp positive reference voltage 1 2.5 2.75 v v refn negative reference voltage 0 0 0.7 v v iref internal reference voltage 1.95 2 2.05 v t startup startup time 50 s v ain input range (absolute) agnd - 0.3 avdd - 0.3 v conversion range v refn v refp v c ain input capacitance 5 6.4 8 pf
electrical characteristics SPEAR1340 150/200 doc id 023063 rev 4 r ain input mux resistance (total equivalent sampling resistance) 1.5 2 2.5 k t conv conversion time (f adc_clk =14 mhz) 1s conversion time 14 adc_clk cycles inl integral linearity error 1 lsb dnl differential linearity error 0.8 lsb table 57. adc characte ristics (c ontinued) symbol parameters min typ max unit
SPEAR1340 timing characteristics doc id 023063 rev 4 151/200 5 timing characteristics this chapter provides the timing characteristics for the synchronous and asynchronous ips present in SPEAR1340. the timings have been calculated unde r the following operating conditions: in worst case: v= 0.90 v, t = 125 c in best case: v= 1.10 v, t = 40 c in ta b l e 58 you will find an explanation of the symbols us ed in this chapter to describe timing parameters. 5.1 reset timing characteristics note: warm reset can be triggered by software by writing any value to the miscellaneous register sys_sw_res. table 58. symbol definition symbol definition t clk clock period: th e time for a complete clock cycle. t clkhigh high-pulse width: the minimu m amount of time for the high pulse of the clock. t clklow low-pulse width: the minimum amount of time for the low pulse of the clock. t setup (t s ) setup time: the minimum amount of time the data signal should be held steady before the clock event so that the data is reliably sampled. t hold (t h ) hold time: the minimum amount of time the data signal should be held steady after the clock event so that the data is reliably sampled. t d clock-to-output delay: the maximum time required to obtain a valid output after the clock edge. table 59. reset timing characteristics symbol description min unit trp(cold) mresetn pin active low st ate duration for cold reset (startup time from all supplies up and stable). see figure 14: cold reset release on page 149 ) 2ms trp(warm) mresetn pin active low state duration for warm reset (minimum pulse width able to reset the device). see figure 15: warm reset release on page 149 ) 500 s
timing characteristics SPEAR1340 152/200 doc id 023063 rev 4 5.2 adc timing characteristics this section describes the timing characterist ics of the touch_xy_sel signal of the a/c converter. the touch_xy_sel signal allows the switching of the x and y axes. it is generated in both cases of 2 and 4 channels (depending on single or dual touchscreen configuration). this signal is high when converting the x values, while low when converting the y ones. figure 16 shows the touch_xy_sel behavior during the adc conversion phase. in this example, the dual touchscreen configuration is used: channels 1 and 3 convert the x values, while channels 6 and 7 convert the y values. figure 16. touchscreen signal waveform 5.3 cortex-a9 jtag/trace timing characteristics this section describes the timing characteristics of cortex-a9 jtag and cortex-a9 trace. 5.3.1 cortex-a9 jtag timing characteristics this section describes the timing char acteristics for the cortex-a9 jtag. the timing characterization is performed assuming an output load capacitance of 20 pf on arm_tdo output and an input transition of 2 ns on all the inputs. figure 17. jtag timing waveforms adc_clk adc_en adc_ s el touch_xy_ s el 01 3 67 arm_tck (input) arm_tdo (output) t clkhigh t clklow t dmin t h t s arm_tdi, arm_tms, arm_trstn (input) old data valid new data valid t dmax
SPEAR1340 timing characteristics doc id 023063 rev 4 153/200 5.3.2 cortex-a9 trace ti ming characteristics this section describes the timing characterist ics for the arm trace which works on both rising edge and falling edge of the arm_trcclk clock. the timing characterization is performed assuming an output load capacitance of 20 pf on the outputs and using pll1 as the clock source for the timing extractions. figure 18. arm trace timing waveform table 60. jtag timing characteristics symbol description min max unit t clk arm_tck clock period 33.3 ns t clkhigh arm_tck pulse high 10 ? ns t clklow arm_tck pulse low 10 ? ns t d arm_tck to arm_tdo output delay 4 17 ns t sdata setup time for arm_tdi and arm_tms data 6 ns t hdata hold time for arm_tdi and arm_tms data 1 ns t sreset setup time for arm_trstn reset 15 ns t hreset hold time for arm_trstn reset 1 ns table 61. arm trace timing characteristics symbol description min max unit t clk arm_trcclk clock period 8 ns t clkhigh arm_trcclk pulse high 2.9 ? ns t clklow arm_trcclk pulse low 2.9 ? ns t drise arm_trcclk to arm_trcdata0..arm_trcdata31, arm_trcctl output delay -3.7 4 ns t dfall arm_trcclk to arm_trcdata0..arm_trcdata31, arm_trcctl output delay -4 3.7 ns arm_trcclk arm_trcdata arm_trcctl t d t d
timing characteristics SPEAR1340 154/200 doc id 023063 rev 4 5.4 cam timing characteristics this section describes the timing characteristi cs of the four camera input interfaces which can work on the clock rising edge or on the clock falling edge. the timing characterization is performed assuming an input transition of 2 ns on all the inputs and camx_pixclk and using pll1 as the clock source for the timing extractions. figure 19. cam timing waveform 1. x = 1..4. table 62. camx timing characteristics symbol description min max unit t clk camx_pixclk clock period 6.5 ? ns t clkhigh camx_pixclk pulse high 2.9 ? ns t clklow camx_pixclk pulse low 2.9 ? ns cam1 t spos setup time for cam1 data res pect to clock rising edge 5.4 ? ns t hpos hold time for cam1 data respect to clock rising edge -0.7 ? ns t sneg setup time for cam1 data respect to clock falling edge 5.6 ? ns t hneg hold time for cam1 data respect to clock falling edge -0.8 ? ns cam2 t spos setup time for cam2 data res pect to clock rising edge 5.7 ? ns t hpos hold time for cam2 data respect to clock rising edge -0.3 ? ns t sneg setup time for cam2 data respect to clock falling edge 5.9 ? ns t hneg hold time for cam2 data respect to clock falling edge -0.4 ? ns t hpos camx_pixclk (input) camx_data[0..7], camx_vsync, camx_hsync (1) (with polarity configured as rising edge) t clkhigh t clklow t spos camx_data[0..7], camx_vsync, camx_hsync (1) (with polarity configured as falling edge) t hneg t sneg
SPEAR1340 timing characteristics doc id 023063 rev 4 155/200 cam3 t spos setup time for cam3 data res pect to clock rising edge 5.5 ? ns t hpos hold time for cam3 data respect to clock rising edge -0.7 ? ns t sneg setup time for cam3 data respect to clock falling edge 5.6 ? ns t hneg hold time for cam3 data respect to clock falling edge -0.7 ? ns cam4 t spos setup time for cam4 data res pect to clock rising edge 5.5 ? ns t hpos hold time for cam4 data respect to clock rising edge -0.8 ? ns t sneg setup time for cam4 data respect to clock falling edge 5.6 ? ns t hneg hold time for cam4 data respect to clock falling edge -0.9 ? ns table 62. camx timing characteristics (continued) symbol description min max unit
timing characteristics SPEAR1340 156/200 doc id 023063 rev 4 5.5 clcd timing characteristics this section describes the timing characterist ics for the lcd display controller which can work on the clock rising edge or on the clock falling edge. the timing characterization is performed assuming an output load capacitance of 10 pf on all outputs and using pll3 as the clock source for the timing extractions. figure 20. clcd timing waveform 1. lcd_data = lcd_r[0-7], lcd_xr[0-7], lcd_b[0-7], lcd_xb[0-7], lcd_g[0-7], lcd_xg[0-7]. table 63. clcd timing characteristics symbol description min max unit t clk lcd_pclk clock period 6.5 ? ns t clkhigh lcd_pclk pulse high 3 ? ns t clklow lcd_pclk pulse low 3 ? ns t d1 lcd_pclk rising edge to lcd_data, lcd_vsync, lcd_hsync l cd_de output data delay 0.9 5.6 ns t d2 lcd_pclk falling edge to lcd_data, lcd_vsync, lcd_hsync l cd_de output data delay 15.8ns lcd_pclk (output) lcd_data (1) lcd_vsync lcd_hsync lcd_de (with polarity configured as rising edge) t clkhigh t clklow t d1 lcd_data (1) lcd_vsync lcd_hsync lcd_de (with polarity configured as falling edge) t d2
SPEAR1340 timing characteristics doc id 023063 rev 4 157/200 5.6 fsmc timing characteristics this section describes the timing characteristics of the flexible static memory controller. the fsmc can interface nand flash, nor and sram . all the possible scenarios are described below. the timing characterization is performed assuming an output load capacitance of 10 pf on all outputs. 5.6.1 nand flash configurat ion timing characteristics figure 21. nand flash conf iguration timing waveform t ale , t cle , t w , t r and t d are fixed values: they depend only on the internal timings of spear. t set , t hold , t wait and t hiz are programmable timings defined by fsmc registers. they can be calculated as: t set = (set + 1) * t hclk (min value for set is 0) t wait = (wait + 1) * t hclk (min value for wait is 1) t hold = (hold + 1) * t hclk (min value for hold is 1) t hiz = hiz * t hclk (min value for hiz is 0) t hclk = 6 ns (period of the ahb clock, the fsmc input clock) t mem is the output delay of the nand flash. when writing a data, since the nand flash strobes it on the rising edge of fsmc_wen, the user should choose the correct values of set, wait, hold and hiz in order to satisfy the following constraints: t set + t w + t wait - t hiz - t d t setup (nand_flash) t hold + t w - t hclk + t d t hold (nand_flash) fsmc_cexn fsmc_ale_ad17 t hclk - t ale fsmc_wen fsmc_cle_ad16 fsmc_io (out) dataout fsmc_ren fsmc_io (in) datain t wait t set + t w t hiz + t d t hclk - t d t hold + t w t wait t set + t r t hold + t r t mem t mem t hclk - t cle
timing characteristics SPEAR1340 158/200 doc id 023063 rev 4 when reading a data, since the fsmc strobes it 1 hclk cycle before the rising edge of fsmc_ren, the user should choose the correct value of data_st in order to satisfy the following setup constraint: t wait - t mem - t del t setup (fsmc_ffs) tdel is the sum of 2 internal delays of spear: from the fsmc flops to the fsmc_ren pad; from the fsmc_io pads to the fsmc flops. table 64. timings for 8-/16-bit nan d flash configuration on fsmc_ce0n symbol min max unit t ale -1.47 2.44 ns t cle -1.77 1.83 t d (8-bit) -2.76 6.48 t d (16-bit) -2.82 6.48 t w -1.56 2.21 t r -1.29 2.50 table 65. timings for 8-/16-bit nan d flash configuration on fsmc_ce1n symbol min max unit t ale -1.44 2.41 ns t cle -1.76 1.80 t d (8-bit) -2.75 6.45 t d (16-bit) -2.81 6.45 t w -1.50 2.18 t r -1.23 2.47 table 66. internal delays for 8- /16-bit nand flas h configuration symbol min max unit t del (8-bit) 3.82 16.34 ns t del (16-bit) 3.82 16.63 t setup (fsmc_ffs) 0.06 0.49
SPEAR1340 timing characteristics doc id 023063 rev 4 159/200 5.6.2 nor flash con figuration timing characteristics figure 22. nor configuration timing waveform (extended_mode = 0) figure 23. nor configuration timing waveform (extended_mode = 1) fsmc_cexn fsmc_ad[25:0] fsmc_wen fsmc_io (out) dataout fsmc_ren fsmc_io (in) datain address fsmc_rb0 datain strobe t ad t av t addr_st t addr_st + t w t data_st t strobe t addr_st - t hclk + t d t d t d t addr_st t r t mem t mem t mem fsmc_cexn fsmc_ad [25:0] fsmc_wen fsmc_io (out) dataout fsmc_ren fsmc_io (in) datain address fsmc_rb0 t ad t addr_st t av t addr_st + t w t data_st t hold_addr t strobe t addr_st - t hclk + t d t d t r t data_st t hold_addr t addr_st + t r t open_dly t mem t mem
timing characteristics SPEAR1340 160/200 doc id 023063 rev 4 t ad , t av , t d , t w , t r and t strobe are fixed values: they depend only on the internal timings of spear. t addr_st , t hold_addr , t data_st and t oen_dly are programmable timings defined by fsmc registers. they can be calculated as: t addr_st = (addr_st + 1) * t hclk (min value for addr_st is 0) t hold_addr = (hold_addr + 1) * t hclk (min value for hold_addr is 0) t data_st = data_st * t hclk (min value for data_st is 0 for read and 1 for write) t oen_dly = oen_delay * t hclk (when 1, the output enable rises 1 hclk cycle before the chip select) since the data strobe always happens 1 hclk cycle before the rising edge of the chip select, tstrobe can be calculated as: t strobe = t hclk - t w t hclk = 6 ns (period of the ahb clock, the fsmc input clock) t mem is the output delay of the nor flash. the fscm_ren signal can toggle either after the de-assertion of the chip select (extended_mode = 0) or after the addr_st phase (extended_mode = 1). in the 1st case the programmable timings for read and write are unique while in the 2nd case they can be different from each other. when writing a data, since the nor strobes it on the rising edge of fsmc_wen, the user should choose the correct values of data_st (and eventually hold_addr) in order to satisfy the setup constraint: t hclk + t w (+ t hold_addr ) + t data_st - t d t setup (nor_flash) the hold constraint, vice versa, is fixed: t hclk - t w + t d t hold (nor_flash) when reading a data, since the fsmc strobes it 1 hclk cycle before the rising edge of fsmc_ren, the user should choose the correct value of data_st in order to satisfy the following setup constraint: t data_st - t mem - t del t setup (fsmc_ffs) t del is the sum of 2 internal delays of spear: from the fsmc flops to the fsmc_ren pad; from the fsmc_io pads to the fsmc flops.
SPEAR1340 timing characteristics doc id 023063 rev 4 161/200 table 67. timings for 8-/16-bit no r flash configuration on fsmc_ce0n symbol min max unit t ad -2.19 4.33 ns t av -2.79 4.61 t d (8-bit) -2.78 6.40 t d (16-bit) -3.02 6.40 t w -1.66 1.99 t r -1.41 2.27 table 68. timings for 8-/16-bit no r flash configuration on fsmc_ce1n symbol min max unit t ad -1.82 4.60 ns t av -2.43 4.88 t d (8-bit) -2.41 6.67 t d (16-bit) -2.65 6.67 t w -1.30 2.27 t r -1.08 2.55 table 69. internal delays for 8-/16-bit nor flash configuration symbol min max unit t del (8-bit) 4.03 16.25 ns t del (16-bit) 4.01 16.54 t setup (fsmc_ffs) 0.05 0.46
timing characteristics SPEAR1340 162/200 doc id 023063 rev 4 5.6.3 sram configuration timing characteristics figure 24. sram configuration timing waveform t ad , t bl , t d , t w , t r and t strobe are fixed values: they depend only on the internal timings of spear. t addr_st and t data_st are programmable timings defined by fsmc registers. they can be calculated as: t addr_st = (addr_st + 1) * t hclk (min value for addr_st is 0) t data_st = data_st * t hclk (min value for data_st is 0 for read and 1 for write) since the data strobe always happens 1 hclk cycle before the rising edge of the chip select, t strobe can be calculated as: t strobe = t hclk - t w t hclk = 6 ns (period of the ahb clock, the fsmc input clock) t mem is the output delay of the static ram. the fscm_ren signal can toggle either after the de-assertion of the chip select (extended_mode = 0) or after the addr_st phase (extended_mode = 1). in the 1st case the programmable timings for read and write are unique while in the 2nd case they can be different from each other. when writing a data, since the sram strobes it on the rising edge of fsmc_wen, the user should choose the correct values of data_st in order to satisfy the setup constraint: t hclk + t w + t data_st - t d t setup (sram) fsmc_cexn fsmc_ad [25:0] fsmc_wen fsmc_io (out) dataout fsmc_ren fsmc_io (in) datain address fsmc_bl0n_av fsmc_bl1n datain t addr_st + t w t data_st t data_st t addr_st - t hclk + t d t d t mem t mem t mem t r t r t bl t bl t ad t strobe
SPEAR1340 timing characteristics doc id 023063 rev 4 163/200 the hold constraint, vice versa, is fixed: t hclk - t w + t d t hold (sram) when reading a data, since the fsmc strobes it 1 hclk cycle before the rising edge of fsmc_ren, the user should choose the correct value of data_st in order to satisfy the following setup constraint: t data_st - t mem - t del t setup (fsmc_ffs) t del is the sum of 2 internal delays of spear: from the fsmc flops to the fsmc_ren pad; from the fsmc_io pads to the fsmc flops. table 70. timings for 8-/16-bit sram configuration on fsmc_ce0n symbol min max unit t ad -2.19 4.33 ns t bl (16-bit) -2.79 4.80 t d (8-bit) -2.78 6.40 t d (16-bit) -3.02 6.40 t w -1.66 1.99 t r -1.41 2.27 table 71. timings for 8-/16-bit sram configuration on fsmc_ce1n symbol min max unit t ad -1.82 4.60 ns t bl (16-bit) -2.43 5.08 t d (8-bit) -2.41 6.67 t d (16-bit) -2.65 6.67 t w -1.30 2.27 t r -1.08 2.55 table 72. internal delays for 8-/16-bit sram configuration symbol min max unit t del (8-bit) 4.03 16.25 ns t del (16-bit) 4.01 16.54 t setup (fsmc_ffs) 0.05 0.46
timing characteristics SPEAR1340 164/200 doc id 023063 rev 4 5.7 gmac timing characteristics this section describes the ac timing characte ristics for the giga/fast ethernet port. the gmac is designed to support 10, 100 and 1000 mbps ethernet/ieee 802.3 networks. it supports gmii, rmii and mii interfaces. note: for the pin list of the supported interfaces, see ta bl e 5: mac ethernet port multiplexing scheme and ta bl e 15: connectivity - mac phy interface signals description . 5.7.1 gmii transmit timing characteristics the timing characterization is performed assuming an output load capacitance of 10 pf on the output pads and using pll2 as internal clock source or mac_gtxclk125 as external clock source for gmii tx interface timings extraction. these timings are valid for 10, 100 and 1000 mbps operation. figure 25. gmii tx timing waveform mac_gtxclk (output) mac_txd0 - mac_txd7, mac_txen, mac_txer t clkhigh t clklow t d table 73. gmii tx timing characteristics parameter descrip tion conditions (1) min max unit t clk mac_gtxclk clock period 8 ns t clkhigh mac_gtxclk pulse high clock source= mac_gtxclk125@125 mhz (50% ideal duty cycle) 1.5 ns t clklow mac_gtxclk pulse low 1.0 ns t clkhigh mac_gtxclk pulse high clock source= mac_gtxclk125@250 mhz internally divided by 2 2.1 ns t clklow mac_gtxclk pulse low 1.4 ns t clkhigh mac_gtxclk pulse high clock source= pll2 2.2 ns t clklow mac_gtxclk pulse low 1.2 ns t d mac_gtxclk to gmii output data 0.4 5.6 ns 1. characterizations based on external clock sources are performed assuming an ideal 50% duty cycle clock.
SPEAR1340 timing characteristics doc id 023063 rev 4 165/200 5.7.2 gmii receive timing characteristics the timing characterization is performed assuming an input transition of 2 ns on all the inputs and using mac_rxclk as source of clock for gmii rx interface timings extraction. figure 26. gmii rx timing waveform 5.7.3 mii transmit ti ming characteristics the timing characterization is performed assuming an output load capacitance of 10 pf on the output pads and using a 2 ns transition on mac_txclk for interface timings extraction. these timings are valid for 10 and 100 mbps operation. figure 27. mii tx timing waveform table 74. gmii rx timing characteristics parameter description (1) 1. characterizations based on external clock sources are performed a ssuming an ideal 50% duty cycle clock. min max unit t clk mac_rxclk clock period 8 ? ns t clkhigh mac_rxclk pulse high 2.5 ? ns t clklow mac_rxclk pulse low 2.5 ? ns t setup (t s ) setup time for gmii receive data 4 ns t hold (t h ) hold time for gmii receive data 0.5 ns mac_rxd0 C mac_rxd7, mac_rxer, mac_rxdv mac_rxclk (input) t h t clkhigh t clklow t s mac_txclk (input) mac_txd0 - mac_txd3, mac_txen, mac_txer t clklow t clkhigh t d
timing characteristics SPEAR1340 166/200 doc id 023063 rev 4 5.7.4 mii receive ti ming characteristics the timing characterization is performed assuming an input transition of 2 ns on all the inputs. these timings are valid for 10 and 100 mbps operation. figure 28. mii rx timing waveform table 75. mii tx timing characteristics symbol description min max unit t clk mac_txclk clock period 40 ? ns t clkhigh mac_txclk pulse high 12 ? ns t clklow mac_txclk pulse low 12 ? ns t d mac_txclk to mii output data 5.1 18 ns table 76. mii rx timing characteristics symbol description min max unit t clk mac_rxclk clock period 40 ? ns t clkhigh mac_rxclk pulse high 12 ? ns t clklow mac_rxclk pulse low 12 ? ns t s setup time for mii receive data 3.8 ns t h hold time for mii receive data 0 t h mac_rxclk (input) mac_rxd0-mac_rxd3, mac_rxer, mac_rxdv t clkhigh t clklow t s
SPEAR1340 timing characteristics doc id 023063 rev 4 167/200 5.7.5 mac ethernet asynchronous sign als timing characteristics (mac_crs and mac_col) mac_crs and mac_col signals are used only by the gmii and mii interfaces. figure 29. mac asynchronous input signals timing waveform 5.7.6 mac serial management channel timing characteristics (mdio/mdc) the mac_mdio and mac_mdc signals are used to perform serial management channel timing. the mdc frequency should be eq ual to or less than 2.5 mhz to be compliant with the ieee 802.3 mii specification. however, mac can function correctly with a maximum mdc frequency of 15 mhz. figure 30. mac_mdc/mac_mdio timing waveform table 77. mac asynchronous input signals timing characteristics symbol description min max unit t d mac_crs to mac_col minimum pulse width 3 - ns mac_crs, mac_col t d table 78. mac_mdc/mac_mdio timing characteristics symbol description min max unit t clk mac_mdc clock period 200 ? ns t d falling edge of mdc to mdio output delay (1) 10 20 ns t clkhigh mac_mdc pulse width high 60 ns mac_mdio (input) mac_mdc (output) t h mac_mdio (output) t d t s t clklow t clkhigh
timing characteristics SPEAR1340 168/200 doc id 023063 rev 4 5.8 gpio/xgpio timing characteristics for edge-sensitive signals, the interrupt line is sampled by flip flops clocked by pclk for gpios and hclk for xgpios, the apb and ahb clocks, normally running at 83 mhz and 166 mhz respectively. the minimum pulse width required for interrupt detection on signal edge is: 3*t pclk (36 ns at 83 mhz) for gpio 3*t hclk (18 ns at 166 mhz) for xgpio 5.9 i2c timing characteristics the timing of high and low level of scl (tsclhigh and tscllow) are programmable. figure 31. i2c timing waveform t clklow mac_mdc pulse width low 60 ns t s setup time for mdio input 30 ns t h hold time for mdio input 0 ns 1. when mdio is used as output, the data is launc hed on the falling edge of the clock as shown in figure 30 . table 78. mac_mdc/mac_mdio timing characteristics (continued) symbol description min max unit i2cx_scl i2cx_sda tsclhigh tsu-sta thd-sta tsu-dat tsu-sto thd-sto tscllow
SPEAR1340 timing characteristics doc id 023063 rev 4 169/200 t hclk is the clock period of the hclk internal clock. the frequency is programmable, for details refer to the rcg section of rm0078, reference manual, SPEAR1340 architecture and functionality . for the i2c working as slave, the only significant parameters are tsu-dat and thd-dat. table 79. timing characteristics for i2c in high-speed mode parameter min (1) 1. hs_scl_hcnt = 10, hs_scl_lcnt = 33, fs_scl_hcnt = 183, fs_scl_lcnt = 233, ic_sda_hold=1 t su-sta (hs_scl_hcnt+7)*t hclk t hd-sta (hs_scl_lcnt+2)*t hclk t su-dat tscllow - t hd-datmax t hd-dat (ic_sda_hold)* t hclk t su-sto (fs_scl_hcnt+7)*t hclk t hd-sto 685*t hclk table 80. time characteristics for i2c in fast-speed mode parameter min (1) 1. scl_hcnt = 183, scl_lcnt = 233 ic_sda_hold=1 t su-sta (scl_hcnt+7)*t hclk t hd-sta (scl_hcnt+3)*t hclk t su-dat t scllow - t hd-datmax t hd-dat (ic_sda_hold)* t hclk t su-sto (scl_hcnt+7)*t hclk t hd-sto 685*t hclk table 81. timing characteristics for i2c in standard-speed mode parameter min (1) 1. scl_hcnt = 664, scl_lcnt = 780 ic_sda_hold=1 t su-sta (scl_lcnt+7)*t hclk t hd-sta (scl_hcnt+3)*t hclk t su-dat t scllow - t hd-datmax t hd-dat (ic_sda_hold)* t hclk t su-sto (scl_hcnt+7)*t hclk t hd-sto 685*t hclk
timing characteristics SPEAR1340 170/200 doc id 023063 rev 4 5.10 i2s timing characteristics this section describes the timing characteristics for the two i2s digital audio ports (i2s_in and i2s_out). the timing characterization is performed assuming an input transition of 2 ns on all the inputs, an output load capacitance of 10 pf on all outputs and using pll1 as source of i2s out_bitclk with a nominal period of 40 ns. i2s transmit timing characteristics figure 32. i2s transmit timing waveform table 82. i2s transmit timing characteristics symbol description min max unit t clk i2s_out_bitclk clock period 40 ? ns t clkhigh i2s_out_bitclk pulse high 15 ? ns t clklow i2s_out_bitclk pulse low 15 ? ns f ovrclk i2s_out_oversam p_clk frequency f i2s_out_bitclk /2 t ovrclkhigh i2s_out_oversamp_cl k pulse high 7.5 ? ns t ovrclkclklo w i2s_out_oversamp_cl k pulse low 7.5 ? ns t d i2s_out_bitclk to i2s_out data delay 13 30 ns i2s_out_bitclk i2s_out_data3 C i2s_out_data0, i2s_out_ws t clkhigh t clklow t d i2s_out_ovrsamp_clk
SPEAR1340 timing characteristics doc id 023063 rev 4 171/200 i2s receive timing characteristics figure 33. i2s receive timing waveform table 83. i2s receive timing characteristics symbol description min max unit t clk i2s_in_bitclk clock period 40 ? ns t clkhigh i2s_in_bitclk pulse high 15 ? ns t clklow i2s_in_bitclk pulse low 15 ? ns t s i2s_in_data, i2s_in_ws setup time 6 ns t h i2s_in_data, i2s_ in_ws hold time 0 ns t h i2s_in_bitclk i2s_in_data3 C i2s_data0, i2s_in_ws t clkhigh t clklow t s
timing characteristics SPEAR1340 172/200 doc id 023063 rev 4 5.11 mcif timing characteristics 5.11.1 synchronous mo de (sd/sdio/mmc) this section describes the timing characteri stics for mcif when interfacing sd/sdio/mmc synchronous memories. the tables below show the timings for the high-speed and full-speed modes. the timing characterization is performed assuming an output load capacitance of 10 pf on all the outputs, an input transition of 2ns on all the inputs and using pll1 as source of the clock used for the timings extraction. the mci_addr_cle_clk signal is programm able via the mcif registers. refer to rm0089, reference manual, spear1 340 address map and registers figure 34. mcif - sd/sdio/ mmc mode timing waveform 1. mcif_out/mcif_in synchronous signals: mcif_dat a0, mcif_data[7..4], mcif_datax_sd (x= 1..3), mcif_sd_cmd table 84. mcif - sd/sdio high sp eed mode timing characteristics symbol description min max unit t clk mcif_addr1_cle_clk clock period 20 ? ns t clkhigh mcif_addr1_cle_clk pulse high t clk /2-1 ? ns t clklow mcif_addr1_cle_clk pulse low t clk /2-1 ? ns t d mcif_addr1_cle_clk to mcif_out output delay 0.2 6.1 ns t s setup time for mcif_in data 14 ns t h hold time for mcif_in data 1.3 ns table 85. mcif - sd/sdio full speed mode timing characteristics symbol description min max unit t clk mcif_addr1_cle_clk clock period 40 ? ns t clkhigh mcif_addr1_cle_clk pulse high t clk /2-1 ? ns mcif_addr1_cle_clk (output) mcif_out (output) (1) mcif_in (input) (1) t clkhigh t clklow t h t su t d
SPEAR1340 timing characteristics doc id 023063 rev 4 173/200 t clklow mcif_addr1_cle_clk pulse low t clk /2-1 ? ns t d mcif_addr1_cle_clk to mcif_out output delay 20.1 25.9 ns t s setup time for mcif_in data 14 ns t h hold time for mcif_in data 0 ns table 86. mcif - mmc high speed mode timing characteristics symbol description min max unit t clk mcif_addr1_cle_clk clock period 20 ? ns t clkhigh mcif_addr1_cle_clk pulse high t clk /2-1 ? ns t clklow mcif_addr1_cle_clk pulse low t clk /2-1 ? ns t d mcif_addr1_cle_clk to mcif_out output delay 0.2 6.1 ns t s setup time for mcif_in data 14 ns t h hold time for mcif_in data 1.3 ns table 87. mcif - mmc full speed mode timing characteristics symbol description min max unit t clk mcif_addr1_cle_clk clock period 40 ? ns t clkhigh mcif_addr1_cle_clk pulse high t clk /2-1 ? ns t clklow mcif_addr1_cle_clk pulse low t clk /2-1 ? ns t d mcif_addr1_cle_clk to mcif_out output delay 20.1 25.9 ns t s setup time for mcif_in data 14 ns t h hold time for mcif_in data 0 ns table 85. mcif - sd/sdio full speed mode timing characteristics (continued) symbol description min max unit
timing characteristics SPEAR1340 174/200 doc id 023063 rev 4 5.11.2 compactflash true id e pio mode/udma mode this section describes the timing characteristics for mcif when interfacing compactflash in true ide mode pio mode and udma mode. the data in ta bl e 88 has been measured in the following configuration: ? true ide pio mode = mode 6 ? hclk period = 6 ns ? cf/xd (clk_xin) base clock period obtained by programming the misc register mcif_cfxd_clk_synt. ?t clk_xin = t ? t0 is the minimum total cycle time. t0 must satisfy the following constraint t0 t2 + t2i t2 is the minimum command active time. t2i is the minimum command active recovery time or command inactive time. figure 35. mcif - cf true ide pio mode waveform table 88. mcif - cf true ide pio mode timing characteristics symbol description min max unit t 0 cycle time 18*t ns t 1 address valid to iord/iowr setup 2*t ns t 2 iord/-iowr 10*t ns t 2i iord/-iowr recovery time 8*t ns t 3 iowr data setup 9.5*t ns t 4 iowr data hold t - 3.2 ns t 5 iord data setup 5 (1) 1. t5 and t6 are the minimum timing requirements the external card has to re spect in order to ensure correct read data sampling inside SPEAR1340. ns t 6 iord data hold 4 (1) ns t 0 t 4 t 3 dataout datain t 2 t 5 t 6 t 1 t 2 i mcif_addr2, mcif_addr1_cle_clk mcif_addr0_ale mcif_ncs0_nce mcif_ncs1 mcif_niowr_nwe mcif_niord_nre mcif_data[15:0] mcif_data[15:0]
SPEAR1340 timing characteristics doc id 023063 rev 4 175/200 figure 36. mcif - cf true ide udma mode waveform 5.12 mpmc timing characteristics this section describes the timing characterist ics for the multiport ddr controller. the ddr interface is designed to support the following standards: ddr3-800 and ddr3-1066 standards, as defined in the jesd79-3e jedec standard. all ddr2 standards: ddr2-1066, ddr2 -800, ddr2-667, ddr2-533, ddr2-400. note: for more information on jedec standards, refer to jedec website: www.jedec.org. this section provides the timing specifications for ddr3 and for ddr2. for ddr3 the timing values reported below can been obtained only upon successfully completing the procedure of leveling. leveling is mandatory for the fly-by topology used for sdram cuts on the pcb. the fly-by topology for the commands, addresses, control signals, and clocks allows better signal integrity. for ddr2 you have to use a t branch topology and you have to calibra te the boar d without the support of the leveling. the ddr phy is an 8-clock sampling-based architecture. the eight clocks are equally delayed across a clock period equal to the phy?s core clock. the clocks are generated from dedicated internal dlls (dll_clocks). table 89. trueide ultra dma timing characteristics symbol item min max unit t dh data hold time (from strobe edge until data become invalid) t ns t ds data setup time ( the time from data valid until strobe edge) 2*t t cyc cycle time (the time from strobe edge to strobe edge) >t dh +t ds =3*t t 2cyc two cycle times ( the time from rising edge to next rising edge or from falling edge to next falling edge of strobe) 2*t cyc >6*t mcif_data[15:0] t 2cyc mcif_niord_nre (strobe) t cyc t cyc t dh t dh t dh t ds t ds
timing characteristics SPEAR1340 176/200 doc id 023063 rev 4 the timings have been calculated in best and worst case, without considering the pads contribution. these are the operating co nditions used for the characterization: in worst case: v=1.10 v, t=125 c in best case: v=1.30 v, t= -40 c addr/ctrl timing characteristics the memory clock (mem_clk) is derived from a fixed dedicated pll output. address and control signals (mem_ctl) are launched on the negative edge of the mem_clk (+/- 1/8 * tmem_clk) in order to have the control signals centered on the rising edge of the clock at memory side (assuming the same board flight-time delay for mem_clk and mem_ctl). the address and control signals have the same output stage, but they present a skew of about 114 ps due to the physical implementation. for a frequency of 533.3 mhz, the period of the clock is t clk = 1.875 ns. the setup time is calculated considering: maximum error = 235 ps maximum data skew = 114 ps ts calculation formula ts= tclk/2?data_skew ?max_error= 938 ps ? 114 ps ? 235 ps= 589 ps the hold time, instead, is calculated considering: maximum error = 0 ps maximum data skew = 114 ps th calculation formula th= tclk/2?data_skew + max_error= 938 ps ? 114 ps + 0 ps= 824 ps table 90. addr/ctrl timing characteristics symbol description value unit t clk mem_clk period 1.875 ns t s setup time for addr/ctrl receive data 589 ps t h hold time for addr/ctrl receive data 824 ps
SPEAR1340 timing characteristics doc id 023063 rev 4 177/200 figure 37. addr/ctrlsi gnals timing waveform write dqs timing characteristics the ddr3 sdram supports a write-leveling feat ure to allow the controller to compensate the skew between the mem_clk and the data strobe (dqs) at each memory cut. during the write leveling phase, the controller uses the feedback from the ddr3 sdram to adjust the dqs to mem_clk relationship. the dqs delay established through this procedure helps to ensure tdqss specifications in systems us ing a fly-by topology by deskewing the trace length mismatch. based on the 8-phase phy architecture, the dqs signal is derived from one of the eight dll_clocks, so it is adjustable with a minimum step of 1/8 of the clock period (max_error). the sampled value coming from the memory is processed so that the tdqss value can vary from 0 to 1/8 tclk (see figure 38 ). for the ddr2 you have to find the right alignment without the write-leveling support. figure 38. dqs strobe timing waveform write dq/dm timing characteristics similar to the creation of the write dqs signal, the write dq/dm signals are created through a clock derived from one of the eight dll_clocks. the clock generating dq/dm signals should always be set two phases before the clock generating dqs. this would ensure a 90-degree phase difference between dq and dqs. due to the path delay difference between dq and dqs, the maximum error respect to the ideal case is one phase off, so the max error is 1/8 tclk. the maximum skew among the dq/dm signals in a single data slice is about 30 ps. for a frequency of 533.3 mhz, the period of the clock is t clk = 1.875 ns. mem_clk addr/ctrl m a x error m a x error t s th s kew s kew mem_clk dq s tdq ss
timing characteristics SPEAR1340 178/200 doc id 023063 rev 4 the setup time is calculated considering: maximum error = 235 ps maximum data skew = 30 ps ts calculation formula ts= tclk/4?data_skew ?max_error= 469 ps ? 30 ps ? 235 ps= 204 ps the hold time, instead, is calculated considering: maximum error = 0 ps maximum data skew = 30 ps th calculation formula th= tclk/4?data_skew + max_error= 469 ps ? 30 ps + 0 ps= 439 ps figure 39. dqs strobe and dq/dm signals timing waveform read dqs and dq timing characteristics the ddr phy is a sampling-based architecture; this means that the inco ming dqs and dq signals are sampled by each of the eight dll_clocks. dm signals are not used for reading. for dqs strobe, a pattern of ?000111? is used to detect a rising edge and a pattern of ?111000? is used to detect a falling edge. the maximum er ror to detect t hese edges is 1/8 tclk. the incoming dq data is sampled, then the sampled data is analyzed in a window of 4 sampled bits relative to detected dqs edges. the maximum skew, without the contribution of the pads, between the dq signals in a single data slice is about 20 ps. for a frequency of 533.3 mhz, the period of the clock is t clk = 1.875 ns. table 91. dq/dm signals timing characteristics symbol description value unit t clk mem_clk period 1.875 ns t s setup time for dq/d m receive data 204 ps t h hold time for dq/dm receive data 439 ps dq s dq/dm ide a l po s ition t s th m a x error d a t a s kew
SPEAR1340 timing characteristics doc id 023063 rev 4 179/200 the setup time is calculated considering: maximum error = 235 ps maximum data skew = 20 ps ts calculation formula ts= tclk/4?data_skew ?max_error= 469 ps ? 20 ps ? 235 ps = 214 ps the hold time, instead, is calculated considering: maximum error = 0 ps maximum data skew = 20 ps th calculation formula th= tclk/4-data_skew + max_error= 469 ps ? 20 ps + 0 ps = 449 ps figure 40. dqs and dq signals timing waveform table 92. dqs and dq signals timing characteristics symbol description value unit t clk mem_clk period 1.875 ns t s setup time for dqs/dq receive data 214 ps t h hold time dqs/dq receive data 449 ps s ign a l s a t memory interf a ce dq s dq d0 d1 d2 d 3 s ign a l s a t phy interf a ce dq s sa mpled p a ttern dq s edge detection m a x error th dq s dq t s d a t a s kew dq sa mpled p a ttern nomin a l center of dq window d0 d1 d2 d 3 01 00 000 11 111 111 1
timing characteristics SPEAR1340 180/200 doc id 023063 rev 4 5.13 pwm timing characteristics this section describes the timing characteristics of the four pwm generators. the timing characterization is performed assuming an output load capacitance of 2 to 10 pf on the four outputs. 5.14 smi timing characteristics this section describes the timing characteri stics of the serial nor flash controller. the timing characterization is performed assuming an output load capacitance of 10 pf on all outputs, an input transition of 2ns on all the inputs and using pll1 as source of the clock for the timing extraction. figure 41. smi timing waveform table 93. pwm timing characteristics symbol parameter min max unit t w pulse width (t= programmed pulse width) t ? 2.2 t + 2.2 ns table 94. smi timing characteristics symbol description min max unit t clk smi_clk clock period 24 ? ns t clkhigh smi_clk output pulse high t/2 - 1 ? ns t clklow smi_clk output pulse low t/2 - 1 ? ns t d smi_clk out to smi_data out output delay 0.81 9.65 ns t s setup time for smi_datain data 3.72 ? ns t h hold time for smi_datain data -6.46 ? ns smi_clk (output) smi_dataout t clkhigh t clklow t d t h t s smi_datain t csf smi_cs0n,smi_cs1n t csr
SPEAR1340 timing characteristics doc id 023063 rev 4 181/200 5.15 ssp timing characteristics this section describes the timing characte ristics of the synchronous serial port. the timing characterization is performed assuming an input transition of 2 ns on all the inputs and an output load capacitance of 10 pf on all outputs and using pll1 as the clock source for the timing extraction. note: the characterization of the ssp ha s been done using the spi protocol. figure 42. ssp_sck waveform the clock polarity parameter (spo) indicates the state of the clock signal when it is idle. this can be programmed in th e sspcr0 register (refer to rm0089, reference manual, SPEAR1340 addre ss map and registers ). t csf min and max delay of falling edge of smi_clk to falling edge of smi_cs0n and smi_cs1n 0.75 9.60 ns t csr min and max delay of rising edge of smi_clk to rising edge of smi_cs0n and smi_cs1n (1) 0.75+t hclk 9.60+t hclk ns 1. t hclk is the period of the programmable hclk clock table 94. smi timing characteristics (continued) symbol description min max unit spo= 0 the clock idle state is low. spo= 1 the clock idle state is high. t ssp_sck(h) t ssp_sck ss p_ s ck ( s po=0) ss p_ s ck ( s po=1) t ssp_sck(l)
timing characteristics SPEAR1340 182/200 doc id 023063 rev 4 5.15.1 spi master mode timings ssp_sck is the spi output clock. the ssp_sc k frequency is progra mmable and derived from pclk, for details refer to the ssp section of the rm0078, reference manual, SPEAR1340 architecture and functionality . figure 43. spi master mode external timing waveform ( sph= 0, spo =0 ) table 95. spi master mode timi ng characterist ics of ssp_sck symbol parameters min max unit t ssp_sck ssp_sck clock period 48 programmable ns t ssp_sck(h) ssp_sck clock high pulse width (t ssp_sck /2) - 1 (t ssp_sck /2) + 1 t ssp_sck(l) ssp_sck clock low pulse width (t ssp_sck /2) - 1 (t ssp_sck /2) + 1 table 96. spi master mode timing characteristics (sph = 0, spo=0) symbol parameters min max unit t su setup time, miso (input) valid before ssp_sck (output) rising edge 17 ns t h hold time, miso (input) valid after ssp_sck (output) rising edge 0 t d1 delay time, ssp_ss#n (output) falling edge to first ssp_sck (output) rising edge t ssp_sck -8 t ssp_sck -2 ns t d2 delay time, ssp_sck ( output) falli ng edge to mosi (output) transition -4.64 12.4 ns t d3 delay time, ssp_sck (output) rising edge to ssp_ss#n (output) rising edge t ssp_sck + 2 t ssp_sck +8 data m s b in l s b in l s b out data m s b out ss p_ ss #n ss p_ s ck ( s po=0) ss p_mi s o (inp u t) ss p_mo s i (o u tp u t) t s u t h t d2 t d1 t d 3
SPEAR1340 timing characteristics doc id 023063 rev 4 183/200 figure 44. spi master mode external timing waveform ( sph= 0, spo =1 ) figure 45. spi master mode external timing waveform (sph = 1, spo = 0) table 97. spi master mode timing characteristics (bit sph = 0, spo=1) symbol parameters min max unit t su setup time, miso (input) valid before ssp_sck (output) falling edge 17.8 ns t h hold time, miso (input) valid after ssp_sck (output) falling edge 0 t d1 delay time, ssp_ss#n (output) falling edge to first ssp_sck (output) falling edge t ssp_sck -8 t ssp_sck -2 ns t d2 delay time, ssp_sck (output) rising edge to mosi (output) transition -3.8 12.5 ns t d3 delay time, ssp_sck ( output) falli ng edge to ssp_ss#n (output) rising edge t ssp_sck + 2 t ssp_sck +8 data m s b in l s b in l s b out data m s b out ss p_ ss #n ss p_ s ck ( s po=1) ss p_mi s o (inp u t) ss p_mo s i (o u tp u t) t s u t d1 t h t d 3 t d2 data m s b in l s b in l s b out data m s b out ss p_ ss #n ss p_ s ck ( s po=0) ss p_mi s o (inp u t) ss p_mo s i (o u tp u t) t s u t h t d2 t d 3 t d1
timing characteristics SPEAR1340 184/200 doc id 023063 rev 4 figure 46. spi master mode external timing waveform (sph = 1, spo = 1) 5.15.2 spi slave mode timings table 98. spi master mode timing characteristics (clock phase bit sph = 1, spo=0) symbol parameters min max unit t su setup time, miso (input) valid before ssp_sck (output) falling edge 17.8 ns t h hold time, miso (input) valid after ssp_sck (output) falling edge 0 t d1 delay time, ssp_ss#n (o utput) falli ng edge to first ssp_sck (output) falling edge t ssp_sck -8 t ssp_sck -2 ns t d2 delay time, ssp_sck (output) rising edge to mosi (output) transition -3.8 12.5 ns t d3 delay time, ssp_sck (outpu t) falling edge to ssp_ss#n (output) rising edge t ssp_sck + 2 t ssp_sck +8 table 99. spi master mode timing characteristics (clock phase bit sph = 1, spo=1) symbol parameters min max unit t su setup time, miso (input) valid before ssp_sck (output) rising edge 17 ns t h hold time, miso (input) valid after ssp_sck (output) rising edge 0 t d1 delay time, ssp_ss#n (output) falling edge to first ssp_sck (output) rising edge t ssp_sck -8 t ssp_sck -2 ns t d2 delay time, ssp_sck ( output) falli ng edge to mosi (output) transition -4.64 12.4 ns t d3 delay time, ssp_sck (output) rising edge to ssp_ss#n (output) rising edge t ssp_sck + 2 t ssp_sck +8 data m s b in l s b in l s b out data m s b out ss p_ ss #n ss p_ s ck ( s po=1) ss p_mi s o (inp u t) ss p_mo s i (o u tp u t) t s u t h t d1 t d2 t d 3
SPEAR1340 timing characteristics doc id 023063 rev 4 185/200 table 100. ssp timing characteristics (slave mode) symbol parameters min max unit t ssp_sck ssp_clk_in input clock period 12 * t pclk 254 * 256 * t pclk ns t ssp_sck(h) ssp_sck clock high pulse width (t ssp_sck - t pclk )/2 t ssp_sck(l) ssp_sck clock low pulse width (t ssp_sck - t pclk )/2 t su data input setup time 4 * t ssp_sck t h data input hold time 0 t d data output delay 3 * t ssp_sck 4 * t ssp_sck
timing characteristics SPEAR1340 186/200 doc id 023063 rev 4 5.16 uart timing characteristics t uartclk = 1/f uartclk with f uartclk in mhz f baudrate = the programmed baud rate frequency for information related to baud rate generation, refer to: section 2.14: uart ports . rm0078, reference manual, SPEAR1340 architecture and functionality figure 47. uart transmit and receive waveform note: the above min. and max. values allow a deviation of 1 baud cycle in a single bit time. the accumulated deviation of a uart character frame must not exceed 3/(16*f baudrate ). table 101. uart transmit timing characteristics symbol parameters min max unit t bit uart duration of transmit data bit (b0..b7), parity bit (pbit), start bit, stop bits 1/f baudrate - t uartclk -1 1/f baudrate + t uartclk +1 ns table 102. uart receive timing characteristics symbol parameter conditions min max unit t bit pulse duration of receive data bit (b0 ..b7), parity bit (pbit), start bit, stop bits (1) 1. the time margin is with respect to a single bit accu mulation and not with respect to the whole uart frame. the start bit is sampled after the 8th baud cycle after a low is detected at inpu t, subsequently, each bit is sampled at consecutive 16 baud cycles. baudrate = 6 mbps 1/f baudrate - (t uartclk /2) 1/f baudrate + (t uartclk /2) ns 1/f baudrate -1/ (16*f baudrate ) 1/f baudrate + (16*f baudrate ) ns b0 b1 start bit uarttxd uartrxd stop bit b2 -- - b7 pbit t bit t bit t bit t bit
SPEAR1340 timing characteristics doc id 023063 rev 4 187/200 5.16.1 irda timing characteristics figure 48 and figure 49 show timing waveforms based on 1 start bit, 5 data bits and 1 stop bit. f baudrate = the programmed baud rate frequency t uartclk = 1/f uartclk figure 48. irda transmit timing waveform figure 49. irda receive timing waveform table 103. irda transmit timing characteristics symbol parameter min max unit t txbit irda transmit mode bit duration 1/f baudrate - t uartclk -1 1/f baudrate + t uartclk +1 ns t txpw irda transmit mode pulse width, start bit data bit value 0 (high pulse) (3/16)*1/f baudrate - t uartclk -1 (3/16)*1/f baudrate + t uartclk +1 table 104. irda receive timing characteristics symbol parameter min max unit t rxbit irda receive mode bit duration 1/f baudrate - t uartclk -1 1/f baudrate + t uartclk +1 ns t rxpw irda receive mode pulse width, start bit data bit value 0 (low pulse) (3/16)*1/f baudrate 0 0 0 0 0 1 1 start bit stop bit t txbit t txpw uart_txd (sirout) 0 0 0 0 0 1 1 start bit stop bit uart_rxd (sirin) t rxpw t rxbit
timing characteristics SPEAR1340 188/200 doc id 023063 rev 4 5.17 vip timing characteristics this section describes the timing characte ristics of the video input parallel block. the timing characterization is performed assuming an input transition of 2 ns on all the inputs and using vip_pixclk as source of the clock for the timings extraction. figure 50. vip timing waveform table 105. vip timing characteristics symbol description min max unit t clk vip_pixclk clock period 6.5 ? ns t clkhigh vip_pixclk pulse high 2.9 ? ns t clklow vip_pixclk pulse low 2.9 ? ns t s setup time for vip data 6 ns t h hold time for vip data -0.71 ns t h vip_pixclk (input) vip_r[0..15], vip_g[0..15], vip_b[0..15], vip_vsync, vip_de t clkhigh t clklow t s
SPEAR1340 package information doc id 023063 rev 4 189/200 6 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack ? is an st trademark. table 106. pgba (23 x 23 mm, 0.8 mm pitch) package mechanical data dimensions ref. databook (mm) drawing (mm) min typ max min typ max a 2.06 1.80 1.93 2.06 a1 0.24 0.30 0.40 0.50 a2 0.56 0.56 a4 0.97 0.97 b 0.40 0.50 0.60 0.40 0.50 0.60 d 22.80 23.00 23.20 22.80 23.00 23.20 d1 21.60 21.60 d2 20.00 20.00 e 22.80 23.00 23.20 22.80 23.00 23.20 e1 21.60 21.60 e2 20.00 20.00 e0.8 0.8 f0.7 0.7 ddd 0.20 0.20 eee 0.25 0.25 fff 0.10 0.10
package information SPEAR1340 190/200 doc id 023063 rev 4 figure 51. pgba package - top view
SPEAR1340 package information doc id 023063 rev 4 191/200 figure 52. pgba package - bottom view table 107. pgba (23 x 23 mm, 0.8 mm pitch) package thermal characteristics symbol parameter value unit ja (1) 1. measured on jesd51 2s2p test board. thermal resistance junction-to-ambient 16.5 c/w jb thermal resistance junction-to-board 9 jc thermal resistance junction-to-case 5 jc junction-to-case thermal characterisation parameter 0.23
acronyms SPEAR1340 192/200 doc id 023063 rev 4 appendix a acronyms table 108. list of acronyms acronym definition acp accelerator coherence port adc analog-to-digital converter aes advanced encryption standard ahb amba high speed bus amba advanced microcontroller bus architecture amp asymmetric multiprocessing apb advanced peripheral bus bist built-in self test cbc cipher block chaining cf compact flash cmos complimentary metal-oxide semiconductor cpu central processing unit crc cyclic redundancy check ddr double data rate des data encryption standard dll delay locked loop (when applied to ddr memories) dma direct memory access emi external memory interface ep endpoint etm embedded trace macrocell fifo first-in-first-out fiq fast interrupt request fpga field programmable gate array fsmc flexible static memory controller gb giga bytes gmii gigabit media independent interface gpio general purpose input / output gpu graphics processing unit hlos high-level operating system hmi human machine interface hw hardware irda infrared data association
SPEAR1340 acronyms doc id 023063 rev 4 193/200 irq interrupt request jpeg joint photographic experts group jtag joint test action group kb kilo bytes lcd liquid color display lsb least significant bit mac media access control mb mega bytes mcu microcontroller unit md5 message digest 5 mii media independent interface mmc multimedia card mmu memory management unit msb most significant bit odt on-die termination otg on-the-go (usb) pcie pci express phy physical (device, transceiver, layer) pll real-time operating system ptm program trace macrocell pwm pulse width modulation ram random access memory ras reconfigurable array subsystem rc root complex rf radio frequency rfu reserved for future use rgmii reduced gigabit media independent interface risc reduced instruction set computing rmii reduced media independent interface rom read only memory rtc real-time clock rtos real-time operating system rx receive sata serial ata sha-1 secure hash algorithm table 108. list of acronyms (continued) acronym definition
acronyms SPEAR1340 194/200 doc id 023063 rev 4 sir serial infrared smi serial memory interface smp symmetric multiprocessing soc system-on-chip spi serial peripheral interface spp standard parallel port sram static ram ssp synchronous serial port sstl stub series terminated logic sw software tcm tightly coupled memory tft thin film transistor, a display technology ttl transistor-transistor logic tx transmit uart universal asyn chronous receiver transmitter usb universal serial bus vic vectored interrupt controller wdt watchdog timer xd extreme digital (card standard) table 108. list of acronyms (continued) acronym definition
SPEAR1340 copyright statement doc id 023063 rev 4 195/200 appendix b copyright statement the recipient acknowledges that the use or further commercialization of the st products by the recipient, its customers, subcontractors or end users, may be subject to essential technology iprs. the recipient commits to inform its subcontractors and its customers of the above. the recipient expressly agrees that st shall under no circumstances be responsible for obtaining and maintaining any licenses to any essential technology iprs necessary for the full or partial exploitation of the st products. "essential technology iprs" shall mean any technology and intellectual property thereof which includes but it is not limited to h.264 codec, mpeg-4 / h.263 / sorenson spark decoder, mpeg-2 / mpeg-1 decoder, jpeg codec, vc-1 decoder, rv decoder, vp6 decoder, vp7/vp8 decoder, avs decoder, divx decoder.
revision history SPEAR1340 196/200 doc id 023063 rev 4 7 revision history table 109. document revision history date revision changes 05-apr-2012 1 initial release. 03-aug-2012 2 features ? added sd interface to bullet ?1x memory card interface?. ? changed the bullet related to lcd from ?lcd display controller, up to 1920 x 1200,60 hz, 24 bpp? to ?lcd display controller, incl.support for full hd, 1920 x 1080, 60 hz, 24 bpp? . ? added new sub-bullets ?secure boot support? and ?jtag disable option? under ?security? security. chapter 6: package information updated table 107: pgba (23 x 23 mm, 0.8 mm pitch) package thermal characteristics : ? changed j b value from 8.2 to 9 c/w. ? added j a and jc values. ? added footnote. ? changed table title. chapter 2: device functions section 2.14: uart ports : ? deleted bullet ?support baud rate up to uartclk_max_freq/16?. ? changed bullet ?programmable by software? to ?programmable by software: up to 125 mhz with a maximum baud rate of 7.81 mbps (125/16).? section 2.17: a/d converter (adc) : changed bullet : ?10-bit resolution? to ?10-bit resolution for the analog cell which can be extended up to 17 bits with embedded oversampling techniques performed by the controller? . section 2.24: camera input interfaces (cam) : changed the numbering of camx from ?cam0, cam1, cam2 and cam3? into ?cam1, cam2, cam3 and cam4?. section 2.23: video encoder (venc) : updated the features. section 2.19: general pu rpose i/o (gpio/xgpio) : added information about xgpio169 in the first bullet of ?xgpio main features? section. section 2.37: temperature sensor (thsens) : ? moved ?offset-related? bullet closer to ?measurement range? bullet as they are related. ? removed reference to ?calibration? from the ?offset-related? bullet. section 2.2: multilayer interconnect matrix (busmatrix) : corrected a typo error in ?single interrupt for outband signaling? bullet. section 2.3.1: bootrom : added sd/mmc to the list of booting devices. section 2.1: cpu subsystem :
SPEAR1340 revision history doc id 023063 rev 4 197/200 03-aug-2012 2 (cont?d) replaced ?parity support to detect internal memory failures during runtime? by ?parity support to detect runtime failures for other internal memories?. section 2.34: clock and reset system : corrected a typo error in bullet ?pll2 programmable dithered pll, dedicated for the 125 mhz clock of the gigabit ethernet macs? section 2.4: multiport ddr controller (mpmc) : split bullet ?exclusive and locked accesses support weighted round-robin arbitration scheme support to ensure high memory bandwidth utilization? into 2 separate ones. section 2.9: giga/fast ethernet port (gmac) : deleted the phrase: ?note that this timing information is shared between the two giga ethernet controllers to provide highest precision in ?bridging? operations? , since only one giga ethernet controller is available. section 2.10: pci express controller (pcie) : updated the introduction. section 2.26: i2s digital audio ports (i2s) : removed bullet ?external sclk gating and enable signal? , as sclk is an internal signal. section 2.27: s/pdif digital audio port : removed bullet ?can detect iec-61937 compressed data? and related footnote from the ?input? features group. section 2.20: lcd display controller (clcd) : replaced bullet ?programmable pixel clock frequency up to bus clock frequency? by ?programmable pixel clock frequency up to 148mhz (1080p resolution)?. section 2.22: video decoder (vdec) : ? updated the bullet ?h.263 profile and level? as follows: - added the image size limitation to profile 0 - deleted sub-bullet ?sorenson spark? and added it as a separate bullet ? split bullet ?vp6, vp7 and vp8, versions 0-3? into two bullets: - vp6 and vp7, versions 0-3 - vp8 version 2 (webm) ? added sub-bullet ?baseline interleaved? to bullet ?jpeg, all common sampling formats? . ?bullet ?input image size? : added limitation to standalone mode. ?bullet ?image cropping / digital zoom? : added limitation ?usable only for jpeg or stand-alone mode? . section 2.29: cryptographic co-processor (c3) : ? removed numerical ids (such as id: 0x00001020). ? removed channel 7: empty bullet. section 2.32: general purpose timers (gpt) : corrected ?8-bit timer clock prescaler? to ?4-bit timer clock prescaler? in the first two bullets. section 2.19: general pu rpose i/o (gpio/xgpio) : updated the first paragraph of introduction. section 2.22: video decoder (vdec) : ? changed ?supported video profiles? to ?supported video codecs? . ? updated bullet ?h.264 profile and level?. table 109. document revision history (continued) date revision changes
revision history SPEAR1340 198/200 doc id 023063 rev 4 03-aug-2012 2 (cont?d) section 2.38: one-time programmable antifuse (otp) : updated bank m description. updated section 2.6: flexible static memory controller (fsmc) . section 2.4: multiport ddr controller (mpmc) : added a note at the first bullet referring to a limi tation of maximum memory address space usage. section 2.24: camera input interfaces (cam) : added a note about feature capability. section 2.37: temperature sensor (thsens) : ? changed measurement of junction temperature starting value from 0 to 20 c. ? added typical correction value. chapter 3: pin description updated the introduction. table 3: ball characteristics : ? modified the power supply for usb_uoc_id from ?usb_uoc_vdd3v3? to ?usb_vdd2v5?. ? modified the power supply for usb_uoc_vbus from ?usb_uoc_vdd3v3? to ?5v?. ? added a footnote about xgpio169 inserted description for spdif_in and spdif_out in table 27: audio - s/pdif signals description . updated footnote under figure 6: SPEAR1340 multiplexing scheme . added a footnote to table 16: connectivity - pcie/sata physical interface (miphy) signals description . updated strap5 description in table 37: strapping options . added a footnote related to chip selection and booting in ta bl e 1 1 : memories - fsmc signals description , table 12: memories - smi signals description and table 38: hardware boot selection (strap[0..3]) table 19: connectivity - usb 2.0 phy signals description : updated the description of usb_uoc_vbus adding the phrase ?the voltage range is 0-5.25 v? . chapter 4: electrical characteristics added a reference to an3317 application note at the beginning of the chapter. section 4.3: clocking parameters : ? added table 42: mclk oscillator characteristics and new section : mclk generated from an external clock source . ? added table 44: rtc oscillator characteristics and new section : rtc clock generated from an external clock source . changed i/o types from ttl1, tt l2, ttl3 and pci/3v3 ttl to iotype1, iotype2, iotype3 and iotype4 (throughout document). table 109. document revision history (continued) date revision changes
SPEAR1340 revision history doc id 023063 rev 4 199/200 03-aug-2012 2 (cont?d) updated section 4.4.1: 3v3/2v5/1v8 i/o buffers (iotype1/iotype2/iotype3) and section 4.4.2: iotype4 i/o buffers . updated section 4.5: voltage re gulator characteristics . inserted section 4.7: required external components (moved from pin description chapter). added section 4.6: miphy characteristics updated section 4.10: reset release : ? updated the introduction. ? renamed and updated figure 14: cold reset release . ? added new figure 15: warm reset release . chapter 5: timing characteristics ? added new section 5.1: reset timing characteristics . ? updated the entire chapter (timi ng waveforms and tables for each ip) with new timing information. ? removed rgmii information (see SPEAR1340 errata sheet for more information). 11-oct-2012 3 updated section 2.29: cryptogr aphic co-processor (c3) added infomation on compensation cells ta b l e 2 : headers/abbreviations added i/o compensation cell column to table ta bl e 3 : b a l l characteristics updated table 59: reset timing characteristics updated section 5.7: gmac timing characteristics corrected figure 34: mcif - sd/sdio/mmc mode timing waveform updated t2i in table 88: mcif - cf true ide pio mode timing characteristics updated ssp figure 42 , table 100 added ta bl e 9 5 updated t d3 in figure 43 and figure 44 updated notes below tables in section 5.9: i2c timing characteristics corrected table 41: smi timing waveform updated section 5.16: uart timing characteristics 26-10-2012 4 updated figure 15: warm reset release on page 149 updated table 100: ssp timing characteristics (slave mode) table 109. document revision history (continued) date revision changes
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